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alpha.c, [...]: Use const0_rtx instead of GEN_INT (0). 

* config/alpha/alpha.c, config/arm/arm.c, config/c4x/c4x.c,
	config/fr30/fr30.md, config/frv/frv.c, config/frv/frv.md,
	config/h8300/h8300.c, config/ia64/ia64.c, config/ip2k/ip2k.md,
	config/m32r/m32r.md, config/m68hc11/m68hc11.c,
	config/mips/mips.md, config/mmix/mmix.c,
	config/mn10300/mn10300.c, config/mn10300/mn10300.md,
	config/ns32k/ns32k.c, config/pa/pa.md, config/pdp11/pdp11.c,
	config/rs6000/altivec.md, config/s390/s390.c,
	config/s390/s390.h, config/s390/s390.md, config/sh/sh.c,
	config/sh/sh.h, config/sh/sh.md, config/stormy16/stormy16.c:
	Use const0_rtx instead of GEN_INT (0).  Do the same for other
	constants that are readily available.

From-SVN: r77161
This commit is contained in:
Kazu Hirata 2004-02-03 06:43:59 +00:00 committed by Kazu Hirata
parent 60c81c8995
commit a556fd39ab
27 changed files with 86 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
gcc/ChangeLog
View File

@ -1,3 +1,18 @@
2004-02-03 Kazu Hirata <kazu@cs.umass.edu>
* config/alpha/alpha.c, config/arm/arm.c, config/c4x/c4x.c,
config/fr30/fr30.md, config/frv/frv.c, config/frv/frv.md,
config/h8300/h8300.c, config/ia64/ia64.c, config/ip2k/ip2k.md,
config/m32r/m32r.md, config/m68hc11/m68hc11.c,
config/mips/mips.md, config/mmix/mmix.c,
config/mn10300/mn10300.c, config/mn10300/mn10300.md,
config/ns32k/ns32k.c, config/pa/pa.md, config/pdp11/pdp11.c,
config/rs6000/altivec.md, config/s390/s390.c,
config/s390/s390.h, config/s390/s390.md, config/sh/sh.c,
config/sh/sh.h, config/sh/sh.md, config/stormy16/stormy16.c:
Use const0_rtx instead of GEN_INT (0). Do the same for other
constants that are readily available.
2004-02-03 Kazu Hirata <kazu@cs.umass.edu>
* doloop.c, optabs.c, regmove.c, sched-deps.c,

6
gcc/config/alpha/alpha.c
View File

@ -6100,7 +6100,7 @@ function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
(VOIDmode,
gen_rtvec (2,
gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
GEN_INT (0)),
const0_rtx),
gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
GEN_INT (GET_MODE_SIZE (cmode)))));
}
@ -7845,7 +7845,7 @@ alpha_expand_epilogue (void)
emit_insn (gen_blockage ());
FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
hard_frame_pointer_rtx, GEN_INT (-1))));
hard_frame_pointer_rtx, constm1_rtx)));
}
}
}
@ -9685,7 +9685,7 @@ unicosmk_gen_dsib (unsigned long *imaskP)
have a frame. */
FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
hard_frame_pointer_rtx, GEN_INT (1))));
hard_frame_pointer_rtx, const1_rtx)));
}
}

2
gcc/config/arm/arm.c
View File

@ -5455,7 +5455,7 @@ arm_gen_movstrqi (rtx *operands)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
emit_insn (gen_addsi3 (dst, dst, const2_rtx));
emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
part_bytes_reg = tmp;
}

6
gcc/config/c4x/c4x.c
View File

@ -1077,7 +1077,7 @@ c4x_expand_epilogue(void)
gen_rtx_PLUS
(QImode, gen_rtx_REG (QImode,
AR3_REGNO),
GEN_INT(-1)))));
constm1_rtx))));
RTX_FRAME_RELATED_P (insn) = 1;
/* We already have the return value and the fp,
@ -2359,8 +2359,8 @@ c4x_rptb_insert (rtx insn)
{
/* We can not use the rptb insn. Replace it so reorg can use
the delay slots of the jump insn. */
emit_insn_before (gen_addqi3 (count_reg, count_reg, GEN_INT (-1)), insn);
emit_insn_before (gen_cmpqi (count_reg, GEN_INT (0)), insn);
emit_insn_before (gen_addqi3 (count_reg, count_reg, constm1_rtx), insn);
emit_insn_before (gen_cmpqi (count_reg, const0_rtx), insn);
emit_insn_before (gen_bge (start_label), insn);
LABEL_NUSES (start_label)++;
delete_insn (insn);

12
gcc/config/fr30/fr30.md
View File

@ -810,7 +810,7 @@
{
rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
emit_insn (gen_movsi (reg, GEN_INT (0)));
emit_insn (gen_movsi (reg, const0_rtx));
emit_insn (gen_subsi3 (reg, reg, operands[0]));
emit_insn (gen_movsi (operands[0], reg));
}
@ -818,14 +818,14 @@
{
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_movsi (reg, GEN_INT (0)));
emit_insn (gen_movsi (reg, const0_rtx));
emit_insn (gen_subsi3 (reg, reg, operands[0]));
emit_insn (gen_movsi (operands[0], reg));
}
}
else
{
emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
emit_insn (gen_movsi_internal (operands[0], const0_rtx));
emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
}
DONE;
@ -921,20 +921,20 @@
{
rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
emit_insn (gen_movsi (reg, GEN_INT (-1)));
emit_insn (gen_movsi (reg, constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
}
else
{
rtx reg = gen_reg_rtx (SImode);
emit_insn (gen_movsi (reg, GEN_INT (-1)));
emit_insn (gen_movsi (reg, constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
}
}
else
{
emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
emit_insn (gen_movsi_internal (operands[0], constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
}
DONE;

2
gcc/config/frv/frv.c
View File

@ -9201,7 +9201,7 @@ frv_expand_mclracc_builtin (tree arglist)
static rtx
frv_expand_noargs_builtin (enum insn_code icode)
{
rtx pat = GEN_FCN (icode) (GEN_INT (0));
rtx pat = GEN_FCN (icode) (const0_rtx);
if (pat)
emit_insn (pat);

2
gcc/config/frv/frv.md
View File

@ -5502,7 +5502,7 @@
/* Scale index-low by wordsize. */
scale = gen_reg_rtx (SImode);
emit_insn (gen_ashlsi3 (scale, indx, GEN_INT (2)));
emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
/* Load the address, add the start of the table back in,
and jump to it. */

8
gcc/config/h8300/h8300.c
View File

@ -3867,7 +3867,7 @@ expand_a_rotate (enum rtx_code code, rtx operands[])
/* If the rotate amount is less than or equal to 0,
we go out of the loop. */
emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
QImode, 0, end_label);
/* Initialize the loop counter. */
@ -3876,16 +3876,16 @@ expand_a_rotate (enum rtx_code code, rtx operands[])
emit_label (start_label);
/* Rotate by one bit. */
tmp = gen_rtx_fmt_ee (code, mode, dst, GEN_INT (1));
tmp = gen_rtx_fmt_ee (code, mode, dst, const1_rtx);
emit_insn (gen_rtx_SET (mode, dst, tmp));
/* Decrement the counter by 1. */
tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
tmp = gen_rtx_PLUS (QImode, counter, constm1_rtx);
emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
/* If the loop counter is nonzero, we go back to the beginning
of the loop. */
emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
start_label);
emit_label (end_label);

8
gcc/config/ia64/ia64.c
View File

@ -3180,9 +3180,9 @@ ia64_expand_epilogue (int sibcall_p)
It is unclear how to compute that number here. */
if (current_frame_info.n_input_regs != 0)
emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
GEN_INT (0), GEN_INT (0),
const0_rtx, const0_rtx,
GEN_INT (current_frame_info.n_input_regs),
GEN_INT (0)));
const0_rtx));
}
}
@ -7151,7 +7151,7 @@ bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
onto MFI because we will add nops before the
insn. It simplifies subsequent code a lot. */
PATTERN (last)
= gen_bundle_selector (GEN_INT (2)); /* -> MFI */
= gen_bundle_selector (const2_rtx); /* -> MFI */
break;
}
else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
@ -7177,7 +7177,7 @@ bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
{
/* Insert "MII;" template. */
ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
insn);
ia64_emit_insn_before (gen_nop (), insn);
ia64_emit_insn_before (gen_nop (), insn);

22
gcc/config/ip2k/ip2k.md
View File

@ -1087,7 +1087,7 @@
instructions. */
if (! nonimmediate_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
emit_insn (gen_ashlhi3 (operands[0], operands[1], GEN_INT (1)));
emit_insn (gen_ashlhi3 (operands[0], operands[1], const1_rtx));
DONE;
}
")
@ -3154,13 +3154,13 @@
if (INTVAL (operands[2]) == 16)
{
emit_insn (gen_movhi (operands[3], operands[5]));
emit_insn (gen_movhi (operands[4], GEN_INT (0)));
emit_insn (gen_movhi (operands[4], const0_rtx));
}
else
{
operands[6] = GEN_INT (INTVAL (operands[2]) - 16);
emit_insn (gen_ashlhi3 (operands[3], operands[5], operands[6]));
emit_insn (gen_movhi (operands[4], GEN_INT (0)));
emit_insn (gen_movhi (operands[4], const0_rtx));
}
}")
@ -3388,18 +3388,18 @@
emit_insn (gen_movhi (operands[7], operands[11]));
emit_insn (gen_movhi (operands[8], operands[12]));
emit_insn (gen_movhi (operands[9], operands[13]));
emit_insn (gen_movhi (operands[10], GEN_INT (0)));
emit_insn (gen_movhi (operands[10], const0_rtx));
}
else if (INTVAL (operands[2]) == 32)
{
emit_insn (gen_movsi (operands[3], operands[5]));
emit_insn (gen_movsi (operands[4], GEN_INT (0)));
emit_insn (gen_movsi (operands[4], const0_rtx));
}
else
{
operands[6] = GEN_INT (INTVAL (operands[2]) - 32);
emit_insn (gen_ashlsi3 (operands[3], operands[5], operands[6]));
emit_insn (gen_movsi (operands[4], GEN_INT (0)));
emit_insn (gen_movsi (operands[4], const0_rtx));
}
}")
@ -3896,7 +3896,7 @@
operands[6] = GEN_INT (INTVAL (operands[2]) - 8);
emit_insn (gen_lshrqi3 (operands[4], operands[5], operands[6]));
}
emit_insn (gen_movqi (operands[3], GEN_INT (0)));
emit_insn (gen_movqi (operands[3], const0_rtx));
}")
(define_insn "lshrhi3" ; 0 1 2 3 4
@ -4027,7 +4027,7 @@
operands[6] = GEN_INT (INTVAL (operands[2]) - 16);
emit_insn (gen_lshrhi3 (operands[4], operands[5], operands[6]));
}
emit_insn (gen_movhi (operands[3], GEN_INT (0)));
emit_insn (gen_movhi (operands[3], const0_rtx));
}")
;; This occurs frequently in supporting FP among other things,
@ -4258,18 +4258,18 @@
emit_insn (gen_movhi (operands[10], operands[11]));
emit_insn (gen_movhi (operands[9], operands[12]));
emit_insn (gen_movhi (operands[8], operands[13]));
emit_insn (gen_movhi (operands[7], GEN_INT(0)));
emit_insn (gen_movhi (operands[7], const0_rtx));
}
else if (INTVAL (operands[2]) == 32)
{
emit_insn (gen_movsi (operands[4], operands[5]));
emit_insn (gen_movsi (operands[3], GEN_INT (0)));
emit_insn (gen_movsi (operands[3], const0_rtx));
}
else
{
operands[6] = GEN_INT (INTVAL (operands[2]) - 32);
emit_insn (gen_lshrsi3 (operands[4], operands[5], operands[6]));
emit_insn (gen_movsi (operands[3], GEN_INT (0)));
emit_insn (gen_movsi (operands[3], const0_rtx));
}
}")

8
gcc/config/m32r/m32r.md
View File

@ -1743,7 +1743,7 @@
rtx op1 = operands[1];
start_sequence ();
emit_insn (gen_cmp_ltusi_insn (op1, GEN_INT (1)));
emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
emit_insn (gen_movcc_insn (op0));
operands[3] = get_insns ();
end_sequence ();
@ -1797,7 +1797,7 @@
else
emit_insn (gen_xorsi3 (op3, op1, op2));
emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));
emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
emit_insn (gen_movcc_insn (op0));
operands[4] = get_insns ();
end_sequence ();
@ -1932,7 +1932,7 @@
HOST_WIDE_INT value = INTVAL (op2);
if (value >= 2147483647)
{
emit_move_insn (op0, GEN_INT (1));
emit_move_insn (op0, const1_rtx);
DONE;
}
@ -2153,7 +2153,7 @@
HOST_WIDE_INT value = INTVAL (op2);
if (value >= 2147483647)
{
emit_move_insn (op0, GEN_INT (1));
emit_move_insn (op0, const1_rtx);
DONE;
}

6
gcc/config/m68hc11/m68hc11.c
View File

@ -1690,7 +1690,7 @@ expand_prologue (void)
if (size & 1)
emit_insn (gen_addhi3 (stack_pointer_rtx,
stack_pointer_rtx, GEN_INT (-1)));
stack_pointer_rtx, constm1_rtx));
}
/* Create the frame pointer. */
@ -1776,7 +1776,7 @@ expand_epilogue (void)
emit_move_after_reload (scratch, stack_pop_word, scratch);
if (size & 1)
emit_insn (gen_addhi3 (stack_pointer_rtx,
stack_pointer_rtx, GEN_INT (1)));
stack_pointer_rtx, const1_rtx));
}
/* For an interrupt handler, restore ZTMP, ZREG and XYREG. */
@ -1807,7 +1807,7 @@ expand_epilogue (void)
}
emit_move_after_reload (gen_rtx_MEM (HImode,
gen_rtx_PLUS (HImode, addr_reg,
GEN_INT (1))), d_reg, 0);
const1_rtx)), d_reg, 0);
if (return_size > HARD_REG_SIZE)
emit_move_after_reload (gen_rtx_MEM (HImode,
gen_rtx_PLUS (HImode, addr_reg,

8
gcc/config/mips/mips.md
View File

@ -4417,7 +4417,7 @@ dsrl\t%3,%3,1\n\
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val < 0)
operands[2] = GEN_INT (0);
operands[2] = const0_rtx;
else if (val >= 32 * 8)
{
int off = val & 7;
@ -4540,7 +4540,7 @@ dsrl\t%3,%3,1\n\
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val < 0)
operands[2] = GEN_INT (0);
operands[2] = const0_rtx;
else if (val >= 32 * 4)
{
int off = val & 3;
@ -4839,7 +4839,7 @@ dsrl\t%3,%3,1\n\
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val < 0)
operands[2] = GEN_INT (0);
operands[2] = const0_rtx;
else if (val >= 32 * 2)
{
int off = val & 1;
@ -4943,7 +4943,7 @@ dsrl\t%3,%3,1\n\
HOST_WIDE_INT val = INTVAL (operands[1]);
if (val < 0)
operands[2] = GEN_INT (0);
operands[2] = const0_rtx;
else
{
operands[1] = GEN_INT (0x7f);

2
gcc/config/mmix/mmix.c
View File

@ -662,7 +662,7 @@ mmix_function_outgoing_value (tree valtype, tree func ATTRIBUTE_UNUSED)
vec[nregs - 1]
= gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (cmode, first_val_regnum + nregs - 1),
GEN_INT (0));
const0_rtx);
return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nregs, vec));
}

2
gcc/config/mn10300/mn10300.c
View File

@ -366,7 +366,7 @@ print_operand (FILE *file, rtx x, int code)
case 'A':
fputc ('(', file);
if (GET_CODE (XEXP (x, 0)) == REG)
output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
else
output_address (XEXP (x, 0));
fputc (')', file);

4
gcc/config/mn10300/mn10300.md
View File

@ -1074,7 +1074,7 @@
{
rtx target = gen_reg_rtx (SImode);
emit_move_insn (target, GEN_INT (0));
emit_move_insn (target, const0_rtx);
emit_insn (gen_subsi3 (target, target, operands[1]));
emit_move_insn (operands[0], target);
DONE;
@ -1772,7 +1772,7 @@
emit_move_insn (index, plus_constant (operands[0], - INTVAL (operands[1])));
emit_insn (gen_cmpsi (index, operands[2]));
emit_jump_insn (gen_bgtu (operands[4]));
emit_move_insn (index, gen_rtx_ASHIFT (SImode, index, GEN_INT (2)));
emit_move_insn (index, gen_rtx_ASHIFT (SImode, index, const2_rtx));
emit_move_insn (addr, gen_rtx_MEM (SImode,
gen_rtx_PLUS (SImode, table, index)));
if (flag_pic)

4
gcc/config/ns32k/ns32k.c
View File

@ -922,7 +922,7 @@ expand_block_move (rtx operands[])
else if (align == UNITS_PER_WORD)
{
/* insns to copy by words */
emit_insn (gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT (2)));
emit_insn (gen_lshrsi3 (count_reg, bytes_rtx, const2_rtx));
emit_insn (gen_movstrsi1 (GEN_INT (4)));
if (constp)
{
@ -963,7 +963,7 @@ expand_block_move (rtx operands[])
emit_label (aligned_label);
/* insns to copy by words */
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT (2)));
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, const2_rtx));
emit_insn (gen_movstrsi1 (GEN_INT (4)));
/* insns to copy rest */

2
gcc/config/pa/pa.md
View File

@ -4877,7 +4877,7 @@
if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
{
operands[2] = GEN_INT (intval / 2);
operands[3] = GEN_INT (2);
operands[3] = const2_rtx;
}
else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
{

2
gcc/config/pdp11/pdp11.c
View File

@ -702,7 +702,7 @@ output_move_quad (rtx *operands)
}
else if (GET_CODE(operands[1]) == CONST_INT)
{
latehalf[1] = GEN_INT (0);
latehalf[1] = const0_rtx;
}
else
abort();

2
gcc/config/rs6000/altivec.md
View File

@ -571,7 +571,7 @@
/* Generate [-0.0, -0.0, -0.0, -0.0]. */
neg0 = gen_reg_rtx (V4SFmode);
emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
/* Use the multiply-add. */

2
gcc/config/s390/s390.c
View File

@ -2519,7 +2519,7 @@ legitimize_pic_address (rtx orig, rtx reg)
int even = INTVAL (op1) - 1;
op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
op0 = gen_rtx_CONST (Pmode, op0);
op1 = GEN_INT (1);
op1 = const1_rtx;
}
emit_move_insn (temp, op0);

2
gcc/config/s390/s390.h
View File

@ -594,7 +594,7 @@ extern int current_function_outgoing_args_size;
s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
/* In 31-bit mode, we need to mask off the high bit of return addresses. */
#define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff))
#define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
/* Exception handling. */

6
gcc/config/s390/s390.md
View File

@ -547,7 +547,7 @@
[(set (reg 33)
(compare (match_operand:HI 0 "register_operand" "d")
(match_operand:HI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
"tml\t%0,65535"
[(set_attr "op_type" "RX")])
@ -555,7 +555,7 @@
[(set (reg 33)
(compare (match_operand:QI 0 "register_operand" "d")
(match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
"tml\t%0,255"
[(set_attr "op_type" "RI")])
@ -6822,7 +6822,7 @@
if (TARGET_64BIT)
emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
else
emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
emit_insn (gen_ashlsi3 (index, index, const2_rtx));
emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));

12
gcc/config/sh/sh.c
View File

@ -2427,7 +2427,7 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
{
operands[2] = GEN_INT (shift2 + 1);
gen_shifty_op (ASHIFT, operands);
operands[2] = GEN_INT (1);
operands[2] = const1_rtx;
gen_shifty_op (ASHIFTRT, operands);
break;
}
@ -2481,7 +2481,7 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
gen_shifty_op (ASHIFT, operands);
if (kind == 7)
emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
break;
default:
return -1;
@ -3375,7 +3375,7 @@ gen_block_redirect (rtx jump, int addr, int need_block)
return prev;
/* Reorg even does nasty things with return insns that cause branches
to go out of range - see find_end_label and callers. */
return emit_insn_before (gen_block_branch_redirect (GEN_INT (0)) , jump);
return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
}
/* We can't use JUMP_LABEL here because it might be undefined
when not optimizing. */
@ -8413,14 +8413,14 @@ sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
movishori));
emit_insn (gen_rotrdi3_mextr (quad0, quad0,
GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx));
emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
gen_rtx_SUBREG (V2HImode, cxt, 0),
movishori));
emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx));
if (TARGET_LITTLE_ENDIAN)
{
emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
@ -9171,7 +9171,7 @@ sh_expand_t_scc (enum rtx_code code, rtx target)
{
emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
emit_insn (gen_subc (result, result, result));
emit_insn (gen_addsi3 (result, result, GEN_INT (1)));
emit_insn (gen_addsi3 (result, result, const1_rtx));
}
else if (code == EQ || code == NE)
emit_insn (gen_move_insn (result, GEN_INT (code == NE)));

2
gcc/config/sh/sh.h
View File

@ -2097,7 +2097,7 @@ struct sh_args {
#define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
{ \
if (TARGET_SHMEDIA) \
(TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
(TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
gen_reg_rtx (Pmode), 0, \
OPTAB_LIB_WIDEN); \
} while (0)

8
gcc/config/sh/sh.md
View File

@ -4059,7 +4059,7 @@
if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
{
operands[1] = gen_mshflo_l_di (operands[0], operands[0],
GEN_INT (0));
const0_rtx);
break;
}
}
@ -9242,7 +9242,7 @@ mov.l\\t1f,r0\\n\\
emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
}
emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
emit_insn (gen_movqi (operands[0], qi_val));
}
@ -10669,7 +10669,7 @@ mov.l\\t1f,r0\\n\\
rtx scratch = gen_reg_rtx (DImode);
rtx last;
emit_insn (gen_adddi3 (scratch, operands[1], GEN_INT (-1)));
emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
emit_insn (gen_xordi3 (scratch, operands[1], scratch));
emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
emit_insn (gen_nsbdi (scratch, scratch));
@ -10694,7 +10694,7 @@ mov.l\\t1f,r0\\n\\
emit_insn (gen_adddi3 (discratch,
simplify_gen_subreg (DImode, operands[1], SImode, 0),
GEN_INT (-1)));
constm1_rtx));
emit_insn (gen_andcdi3 (discratch,
simplify_gen_subreg (DImode, operands[1], SImode, 0),
discratch));

2
gcc/config/stormy16/stormy16.c
View File

@ -1696,7 +1696,7 @@ xstormy16_expand_casesi (rtx index, rtx lower_bound, rtx range,
emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1,
default_label);
int_index = gen_lowpart_common (HImode, index);
emit_insn (gen_ashlhi3 (int_index, int_index, GEN_INT (2)));
emit_insn (gen_ashlhi3 (int_index, int_index, const2_rtx));
emit_jump_insn (gen_tablejump_pcrel (int_index, table));
}