From a5784ce6249b20197e3082cc592c3640121dc020 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 25 Mar 2013 14:55:05 +0000 Subject: [PATCH] Fix ChangeLog formatting. gcc/ Fix ChangeLog formatting. gcc/testsuite 2013-03-25 Kyrylo Tkachov * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test body from here... * gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here. * gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here... * gcc.target/aarch64/atomic-op-acq_rel.x: ... to here. * gcc.target/aarch64/atomic-op-acquire.c: Move test body from here... * gcc.target/aarch64/atomic-op-acquire.x: ... to here. * gcc.target/aarch64/atomic-op-char.c: Move test body from here... * gcc.target/aarch64/atomic-op-char.x: ... to here. * gcc.target/aarch64/atomic-op-consume.c: Move test body from here... * gcc.target/aarch64/atomic-op-consume.x: ... to here. * gcc.target/aarch64/atomic-op-int.c: Move test body from here... * gcc.target/aarch64/atomic-op-int.x: ... to here. * gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here... * gcc.target/aarch64/atomic-op-relaxed.x: ... to here. * gcc.target/aarch64/atomic-op-release.c: Move test body from here... * gcc.target/aarch64/atomic-op-release.x: ... to here. * gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here... * gcc.target/aarch64/atomic-op-seq_cst.x: ... to here. * gcc.target/aarch64/atomic-op-short.c: Move test body from here... * gcc.target/aarch64/atomic-op-short.x: ... to here. * gcc.target/arm/atomic-comp-swap-release-acquire.c: New test. * gcc.target/arm/atomic-op-acq_rel.c: Likewise. * gcc.target/arm/atomic-op-acquire.c: Likewise. * gcc.target/arm/atomic-op-char.c: Likewise. * gcc.target/arm/atomic-op-consume.c: Likewise. * gcc.target/arm/atomic-op-int.c: Likewise. * gcc.target/arm/atomic-op-relaxed.c: Likewise. * gcc.target/arm/atomic-op-release.c: Likewise. * gcc.target/arm/atomic-op-seq_cst.c: Likewise. * gcc.target/arm/atomic-op-short.c: Likewise. From-SVN: r197051 --- gcc/ChangeLog | 1 + gcc/testsuite/ChangeLog | 34 +++++++++++++++++ .../atomic-comp-swap-release-acquire.c | 36 +----------------- .../atomic-comp-swap-release-acquire.x | 36 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-acq_rel.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-acq_rel.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-acquire.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-acquire.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-char.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-char.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-consume.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-consume.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-int.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-int.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-relaxed.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-relaxed.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-release.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-release.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-seq_cst.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-seq_cst.x | 37 ++++++++++++++++++ .../gcc.target/aarch64/atomic-op-short.c | 38 +------------------ .../gcc.target/aarch64/atomic-op-short.x | 37 ++++++++++++++++++ .../arm/atomic-comp-swap-release-acquire.c | 10 +++++ .../gcc.target/arm/atomic-op-acq_rel.c | 10 +++++ .../gcc.target/arm/atomic-op-acquire.c | 10 +++++ gcc/testsuite/gcc.target/arm/atomic-op-char.c | 10 +++++ .../gcc.target/arm/atomic-op-consume.c | 10 +++++ gcc/testsuite/gcc.target/arm/atomic-op-int.c | 10 +++++ .../gcc.target/arm/atomic-op-relaxed.c | 10 +++++ .../gcc.target/arm/atomic-op-release.c | 10 +++++ .../gcc.target/arm/atomic-op-seq_cst.c | 10 +++++ .../gcc.target/arm/atomic-op-short.c | 10 +++++ 32 files changed, 514 insertions(+), 368 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-char.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-int.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-release.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x create mode 100644 gcc/testsuite/gcc.target/aarch64/atomic-op-short.x create mode 100644 gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-acquire.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-char.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-consume.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-int.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-release.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c create mode 100644 gcc/testsuite/gcc.target/arm/atomic-op-short.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6ecf997ec59..f48ead2329f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -70,6 +70,7 @@ for microMIPS.add3" 2013-03-25 Kyrylo Tkachov + PR target/56720 * config/arm/iterators.md (v_cmp_result): New mode attribute. * config/arm/neon.md (vcond): Handle unordered cases. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 06eb1a6cf10..f6addcf762d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,37 @@ +2013-03-25 Kyrylo Tkachov + + * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Move test + body from here... + * gcc.target/aarch64/atomic-comp-swap-release-acquire.x: ... to here. + * gcc.target/aarch64/atomic-op-acq_rel.c: Move test body from here... + * gcc.target/aarch64/atomic-op-acq_rel.x: ... to here. + * gcc.target/aarch64/atomic-op-acquire.c: Move test body from here... + * gcc.target/aarch64/atomic-op-acquire.x: ... to here. + * gcc.target/aarch64/atomic-op-char.c: Move test body from here... + * gcc.target/aarch64/atomic-op-char.x: ... to here. + * gcc.target/aarch64/atomic-op-consume.c: Move test body from here... + * gcc.target/aarch64/atomic-op-consume.x: ... to here. + * gcc.target/aarch64/atomic-op-int.c: Move test body from here... + * gcc.target/aarch64/atomic-op-int.x: ... to here. + * gcc.target/aarch64/atomic-op-relaxed.c: Move test body from here... + * gcc.target/aarch64/atomic-op-relaxed.x: ... to here. + * gcc.target/aarch64/atomic-op-release.c: Move test body from here... + * gcc.target/aarch64/atomic-op-release.x: ... to here. + * gcc.target/aarch64/atomic-op-seq_cst.c: Move test body from here... + * gcc.target/aarch64/atomic-op-seq_cst.x: ... to here. + * gcc.target/aarch64/atomic-op-short.c: Move test body from here... + * gcc.target/aarch64/atomic-op-short.x: ... to here. + * gcc.target/arm/atomic-comp-swap-release-acquire.c: New test. + * gcc.target/arm/atomic-op-acq_rel.c: Likewise. + * gcc.target/arm/atomic-op-acquire.c: Likewise. + * gcc.target/arm/atomic-op-char.c: Likewise. + * gcc.target/arm/atomic-op-consume.c: Likewise. + * gcc.target/arm/atomic-op-int.c: Likewise. + * gcc.target/arm/atomic-op-relaxed.c: Likewise. + * gcc.target/arm/atomic-op-release.c: Likewise. + * gcc.target/arm/atomic-op-seq_cst.c: Likewise. + * gcc.target/arm/atomic-op-short.c: Likewise. + 2013-03-25 Richard Biener PR middle-end/56694 diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c index 1492e253730..9785bca4f51 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c @@ -1,41 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -#define STRONG 0 -#define WEAK 1 -int v = 0; - -int -atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange (&v, &a, &b, - STRONG, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange (&v, &a, &b, - WEAK, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange_n (&v, &a, b, - STRONG, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} - -int -atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) -{ - return __atomic_compare_exchange_n (&v, &a, b, - WEAK, __ATOMIC_RELEASE, - __ATOMIC_ACQUIRE); -} +#include "atomic-comp-swap-release-acquire.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x new file mode 100644 index 00000000000..4403afd6455 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x @@ -0,0 +1,36 @@ + +#define STRONG 0 +#define WEAK 1 +int v = 0; + +int +atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange (&v, &a, &b, + STRONG, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange (&v, &a, &b, + WEAK, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange_n (&v, &a, b, + STRONG, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} + +int +atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b) +{ + return __atomic_compare_exchange_n (&v, &a, b, + WEAK, __ATOMIC_RELEASE, + __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c index be6682fd894..8569ac0dfc9 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_ACQ_REL (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_sub_ACQ_REL (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_and_ACQ_REL (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_nand_ACQ_REL (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_xor_ACQ_REL (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); -} - -int -atomic_fetch_or_ACQ_REL (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); -} +#include "atomic-op-acq_rel.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x new file mode 100644 index 00000000000..9970bbb2524 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_ACQ_REL (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_sub_ACQ_REL (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_and_ACQ_REL (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_nand_ACQ_REL (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_xor_ACQ_REL (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL); +} + +int +atomic_fetch_or_ACQ_REL (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c index 023797e6f61..57e6d57d5ef 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_ACQUIRE (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_sub_ACQUIRE (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_and_ACQUIRE (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_nand_ACQUIRE (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_xor_ACQUIRE (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); -} - -int -atomic_fetch_or_ACQUIRE (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); -} +#include "atomic-op-acquire.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x new file mode 100644 index 00000000000..7eeb7f84583 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_ACQUIRE (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_sub_ACQUIRE (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_and_ACQUIRE (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_nand_ACQUIRE (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_xor_ACQUIRE (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE); +} + +int +atomic_fetch_or_ACQUIRE (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c index 8dcc4c8c1da..d6c2aa593ba 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -char v = 0; - -char -atomic_fetch_add_RELAXED (char a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_sub_RELAXED (char a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_and_RELAXED (char a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_nand_RELAXED (char a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_xor_RELAXED (char a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -char -atomic_fetch_or_RELAXED (char a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-char.x" /* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x new file mode 100644 index 00000000000..a543aa9e09d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x @@ -0,0 +1,37 @@ +char v = 0; + +char +atomic_fetch_add_RELAXED (char a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_sub_RELAXED (char a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_and_RELAXED (char a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_nand_RELAXED (char a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_xor_RELAXED (char a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +char +atomic_fetch_or_RELAXED (char a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c index e3afde24516..38d6c2cfb2c 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_CONSUME (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_sub_CONSUME (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_and_CONSUME (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_nand_CONSUME (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_xor_CONSUME (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); -} - -int -atomic_fetch_or_CONSUME (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); -} +#include "atomic-op-consume.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x new file mode 100644 index 00000000000..c6b0792ba04 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_CONSUME (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_sub_CONSUME (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_and_CONSUME (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_nand_CONSUME (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_xor_CONSUME (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME); +} + +int +atomic_fetch_or_CONSUME (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c index 065ccf53306..9ad7a794fc9 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELAXED (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_sub_RELAXED (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_and_RELAXED (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_nand_RELAXED (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_xor_RELAXED (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_or_RELAXED (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-int.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x new file mode 100644 index 00000000000..74ab6323c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELAXED (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_sub_RELAXED (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_and_RELAXED (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_nand_RELAXED (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_xor_RELAXED (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_or_RELAXED (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c index 065ccf53306..cd3fe2c3ead 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELAXED (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_sub_RELAXED (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_and_RELAXED (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_nand_RELAXED (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_xor_RELAXED (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -int -atomic_fetch_or_RELAXED (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-relaxed.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x new file mode 100644 index 00000000000..74ab6323c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELAXED (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_sub_RELAXED (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_and_RELAXED (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_nand_RELAXED (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_xor_RELAXED (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +int +atomic_fetch_or_RELAXED (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c index 3d8c49ccbd0..2fc04b210de 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_RELEASE (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_sub_RELEASE (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_and_RELEASE (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_nand_RELEASE (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_xor_RELEASE (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); -} - -int -atomic_fetch_or_RELEASE (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); -} +#include "atomic-op-release.x" /* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x new file mode 100644 index 00000000000..343f09b5264 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_RELEASE (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_sub_RELEASE (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_and_RELEASE (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_nand_RELEASE (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_xor_RELEASE (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE); +} + +int +atomic_fetch_or_RELEASE (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c index a8ad4f807ec..202d471d083 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -int v = 0; - -int -atomic_fetch_add_SEQ_CST (int a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_sub_SEQ_CST (int a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_and_SEQ_CST (int a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_nand_SEQ_CST (int a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_xor_SEQ_CST (int a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); -} - -int -atomic_fetch_or_SEQ_CST (int a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); -} +#include "atomic-op-seq_cst.x" /* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x new file mode 100644 index 00000000000..e654a74e2af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x @@ -0,0 +1,37 @@ +int v = 0; + +int +atomic_fetch_add_SEQ_CST (int a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_sub_SEQ_CST (int a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_and_SEQ_CST (int a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_nand_SEQ_CST (int a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_xor_SEQ_CST (int a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST); +} + +int +atomic_fetch_or_SEQ_CST (int a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c index 30db3405308..39e71c18a93 100644 --- a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c @@ -1,43 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -short v = 0; - -short -atomic_fetch_add_RELAXED (short a) -{ - return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_sub_RELAXED (short a) -{ - return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_and_RELAXED (short a) -{ - return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_nand_RELAXED (short a) -{ - return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_xor_RELAXED (short a) -{ - return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); -} - -short -atomic_fetch_or_RELAXED (short a) -{ - return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); -} +#include "atomic-op-short.x" /* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ /* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x new file mode 100644 index 00000000000..2fd70f59eb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x @@ -0,0 +1,37 @@ +short v = 0; + +short +atomic_fetch_add_RELAXED (short a) +{ + return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_sub_RELAXED (short a) +{ + return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_and_RELAXED (short a) +{ + return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_nand_RELAXED (short a) +{ + return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_xor_RELAXED (short a) +{ + return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED); +} + +short +atomic_fetch_or_RELAXED (short a) +{ + return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c new file mode 100644 index 00000000000..1c1028ce147 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c new file mode 100644 index 00000000000..2f091f29057 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c new file mode 100644 index 00000000000..977c2fab97c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc/testsuite/gcc.target/arm/atomic-op-char.c new file mode 100644 index 00000000000..63e34c1d3e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-char.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c new file mode 100644 index 00000000000..8e1779e2381 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-consume.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc/testsuite/gcc.target/arm/atomic-op-int.c new file mode 100644 index 00000000000..1476c52607a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-int.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c new file mode 100644 index 00000000000..cae83230bd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc/testsuite/gcc.target/arm/atomic-op-release.c new file mode 100644 index 00000000000..ed90aab2edd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-release.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c new file mode 100644 index 00000000000..c7b93eb6d61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc/testsuite/gcc.target/arm/atomic-op-short.c new file mode 100644 index 00000000000..f4d6262e005 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-short.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */