Add Jim's patches to improve reload behaviour.
From-SVN: r22561
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Nick Clifton
Nick Clifton
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@ -1,5 +1,13 @@
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Wed Sep 23 16:22:01 1998 Nick Clifton <nickc@cygnus.com>
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* config/arm/thumb.h: The following patches were made by Jim Wilson:
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(enum reg_class): Add NONARG_LO_REGS support.
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(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGNO_REG_CLASS,
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PREFERRED_RELOAD_CLASS, SECONDARY_RELOAD_CLASS): Likewise.
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(GO_IF_LEGITIMATE_ADDRESS): Disable REG+REG addresses before reload
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completes. Re-enable HImode REG+OFFSET addresses.
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(LEGITIMIZE_RELOAD_ADDRESS): Define.
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* expmed.c (extract_bit_field): Add comment from Jim Wilson.
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Wed Sep 23 13:26:02 1998 Richard Henderson <rth@cygnus.com>
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@ -472,9 +472,15 @@ extern char * structure_size_string;
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#define MODES_TIEABLE_P(MODE1,MODE2) 1
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/* The NOARG_LO_REGS class is the set of LO_REGS that are not used for passing
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arguments to functions. These are the registers that are available for
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spilling during reload. The code in reload1.c:init_reload() will detect this
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class and place it into 'reload_address_base_reg_class'. */
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enum reg_class
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{
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NO_REGS,
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NONARG_LO_REGS,
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LO_REGS,
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STACK_REG,
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BASE_REGS,
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@ -490,6 +496,7 @@ enum reg_class
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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"NONARG_LO_REGS", \
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"LO_REGS", \
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"STACK_REG", \
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"BASE_REGS", \
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@ -500,6 +507,7 @@ enum reg_class
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#define REG_CLASS_CONTENTS \
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{ \
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0x00000, \
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0x000f0, \
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0x000ff, \
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0x02000, \
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0x020ff, \
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@ -509,7 +517,8 @@ enum reg_class
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) == STACK_POINTER_REGNUM ? STACK_REG \
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: (REGNO) < 8 ? LO_REGS \
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: (REGNO) < 8 ? ((REGNO) < 4 ? LO_REGS \
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: NONARG_LO_REGS) \
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: HI_REGS)
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#define BASE_REG_CLASS BASE_REGS
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@ -555,8 +564,15 @@ enum reg_class
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abort. Alternatively, this could be fixed by modifying BASE_REG_CLASS
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to be LO_REGS instead of BASE_REGS. It is not clear what affect this
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change would have. */
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/* ??? This looks even more suspiciously wrong. PREFERRED_RELOAD_CLASS
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must always return a strict subset of the input class. Just blindly
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returning LO_REGS is safe only if the input class is a superset of LO_REGS,
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but there is no check for this. Added another exception for NONARG_LO_REGS
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because it is not a superset of LO_REGS. */
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/* ??? We now use NONARG_LO_REGS for caller_save_spill_class, so the
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comments about BASE_REGS are now obsolete. */
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#define PREFERRED_RELOAD_CLASS(X,CLASS) \
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((CLASS) == BASE_REGS ? (CLASS) \
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((CLASS) == BASE_REGS || (CLASS) == NONARG_LO_REGS ? (CLASS) \
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: LO_REGS)
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/*
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((CONSTANT_P ((X)) && GET_CODE ((X)) != CONST_INT \
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@ -565,9 +581,10 @@ enum reg_class
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&& (unsigned HOST_WIDE_INT) INTVAL ((X)) > 255) ? NO_REGS \
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: LO_REGS) */
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/* Must leave BASE_REGS reloads alone, see comment above. */
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/* Must leave BASE_REGS and NONARG_LO_REGS reloads alone, see comment
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above. */
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
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((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
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((CLASS) != LO_REGS && (CLASS) != BASE_REGS && (CLASS) != NONARG_LO_REGS \
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? ((true_regnum (X) == -1 ? LO_REGS \
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: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
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: NO_REGS)) \
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@ -885,6 +902,16 @@ int thumb_shiftable_const ();
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else if (GET_CODE (X) == PLUS) \
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{ \
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/* REG+REG address can be any two index registers. */ \
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/* ??? REG+REG addresses have been completely disabled before \
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reload completes, because we do not have enough available \
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reload registers. We only have 3 guaranteed reload registers \
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(NONARG_LO_REGS - the frame pointer), but we need at least 4 \
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to support REG+REG addresses. We have left them enabled after \
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reload completes, in the hope that reload_cse_regs and related \
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routines will be able to create them after the fact. It is \
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probably possible to support REG+REG addresses with additional \
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reload work, but I do not not have enough time to attempt such \
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a change at this time. */ \
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/* ??? Normally checking the mode here is wrong, since it isn't \
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impossible to use REG+REG with DFmode. However, the movdf \
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pattern requires offsettable addresses, and REG+REG is not \
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@ -898,14 +925,14 @@ int thumb_shiftable_const ();
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will be replaced with STACK, and SP relative addressing only \
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permits SP+OFFSET. */ \
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if (GET_MODE_SIZE (MODE) <= 4 \
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/* ??? See comment above. */ \
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&& reload_completed \
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&& GET_CODE (XEXP (X, 0)) == REG \
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&& GET_CODE (XEXP (X, 1)) == REG \
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&& XEXP (X, 0) != frame_pointer_rtx \
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&& XEXP (X, 1) != frame_pointer_rtx \
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/* CYGNUS LOCAL nickc */ \
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&& XEXP (X, 0) != virtual_stack_vars_rtx \
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&& XEXP (X, 1) != virtual_stack_vars_rtx \
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/* END CYGNUS LOCAL */ \
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&& REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
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&& REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
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goto WIN; \
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@ -913,9 +940,6 @@ int thumb_shiftable_const ();
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else if (GET_CODE (XEXP (X, 0)) == REG \
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&& (REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
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|| XEXP (X, 0) == arg_pointer_rtx) \
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/* CYGNUS LOCAL nickc */ \
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&& GET_MODE_SIZE (MODE) != 2 \
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/* END CYGNUS LOCAL */ \
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&& GET_CODE (XEXP (X, 1)) == CONST_INT \
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&& LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
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goto WIN; \
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@ -933,6 +957,32 @@ int thumb_shiftable_const ();
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} \
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}
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/* ??? If an HImode FP+large_offset address is converted to an HImode
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SP+large_offset address, then reload won't know how to fix it. It sees
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only that SP isn't valid for HImode, and so reloads the SP into an index
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register, but the resulting address is still invalid because the offset
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is too big. We fix it here instead by reloading the entire address. */
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/* We could probably achieve better results by defining PROMOTE_MODE to help
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cope with the variances between the Thumb's signed and unsigned byte and
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halfword load instructions. */
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#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
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{ \
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if (GET_CODE (X) == PLUS \
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&& GET_MODE_SIZE (MODE) < 4 \
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&& GET_CODE (XEXP (X, 0)) == REG \
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&& XEXP (X, 0) == stack_pointer_rtx \
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&& GET_CODE (XEXP (X, 1)) == CONST_INT \
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&& ! LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
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{ \
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rtx orig_X = X; \
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X = copy_rtx (X); \
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push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
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reload_address_base_reg_class, \
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Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
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goto WIN; \
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} \
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}
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#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
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#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)
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