altivec.h (vec_rlmi): New #define.
[gcc] 2017-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/altivec.h (vec_rlmi): New #define. (vec_vrlnm): Likewise. (vec_rlnm): Likewise. * config/rs6000/altivec.md (UNSPEC_VRLMI): New UNSPEC enum value. (UNSPEC_VRLNM): Likewise. (VIlong): New mode iterator. (altivec_vrl<VI_char>mi): New define_insn. (altivec_vrl<VI_char>nm): Likewise. * config/rs6000/rs6000-builtin.def (VRLWNM): New monomorphic function entry. (VRLDNM): Likewise. (RLNM): New polymorphic function entry. (VRLWMI): New monomorphic function entry. (VRLDMI): Likewise. (RLMI): New polymorphic function entry. * config/rs6000/r6000-c.c (altivec_overloaded_builtin_table): Add new entries for P9V_BUILTIN_VEC_RLMI and P9V_BUILTIN_VEC_RLNM. * doc/extend.texi: Add description of vec_rlmi, vec_rlnm, and vec_vrlnm. [gcc/testsuite] 2017-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * vec-rlmi-rlnm.c: New file. From-SVN: r244546
This commit is contained in:
parent
1e0424d998
commit
a660777486
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@ -1,3 +1,25 @@
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2017-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* config/rs6000/altivec.h (vec_rlmi): New #define.
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(vec_vrlnm): Likewise.
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(vec_rlnm): Likewise.
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* config/rs6000/altivec.md (UNSPEC_VRLMI): New UNSPEC enum value.
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(UNSPEC_VRLNM): Likewise.
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(VIlong): New mode iterator.
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(altivec_vrl<VI_char>mi): New define_insn.
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(altivec_vrl<VI_char>nm): Likewise.
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* config/rs6000/rs6000-builtin.def (VRLWNM): New monomorphic
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function entry.
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(VRLDNM): Likewise.
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(RLNM): New polymorphic function entry.
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(VRLWMI): New monomorphic function entry.
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(VRLDMI): Likewise.
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(RLMI): New polymorphic function entry.
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* config/rs6000/r6000-c.c (altivec_overloaded_builtin_table): Add
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new entries for P9V_BUILTIN_VEC_RLMI and P9V_BUILTIN_VEC_RLNM.
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* doc/extend.texi: Add description of vec_rlmi, vec_rlnm, and
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vec_vrlnm.
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2017-01-17 Jakub Jelinek <jakub@redhat.com>
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2017-01-17 Jakub Jelinek <jakub@redhat.com>
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PR debug/78839
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PR debug/78839
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@ -168,6 +168,9 @@
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#define vec_re __builtin_vec_re
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#define vec_re __builtin_vec_re
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#define vec_round __builtin_vec_round
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#define vec_round __builtin_vec_round
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#define vec_recipdiv __builtin_vec_recipdiv
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#define vec_recipdiv __builtin_vec_recipdiv
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#define vec_rlmi __builtin_vec_rlmi
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#define vec_vrlnm __builtin_vec_rlnm
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#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((b)<<8)|(c)))
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#define vec_rsqrt __builtin_vec_rsqrt
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#define vec_rsqrt __builtin_vec_rsqrt
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#define vec_rsqrte __builtin_vec_rsqrte
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#define vec_rsqrte __builtin_vec_rsqrte
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#define vec_vsubfp __builtin_vec_vsubfp
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#define vec_vsubfp __builtin_vec_vsubfp
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@ -156,6 +156,8 @@
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UNSPEC_CMPRB
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UNSPEC_CMPRB
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UNSPEC_CMPRB2
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UNSPEC_CMPRB2
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UNSPEC_CMPEQB
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UNSPEC_CMPEQB
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UNSPEC_VRLMI
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UNSPEC_VRLNM
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])
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])
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(define_c_enum "unspecv"
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(define_c_enum "unspecv"
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@ -168,8 +170,10 @@
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;; Like VI, defined in vector.md, but add ISA 2.07 integer vector ops
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;; Like VI, defined in vector.md, but add ISA 2.07 integer vector ops
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(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
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(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
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;; Short vec in modes
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;; Short vec int modes
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(define_mode_iterator VIshort [V8HI V16QI])
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(define_mode_iterator VIshort [V8HI V16QI])
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;; Longer vec int modes for rotate/mask ops
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(define_mode_iterator VIlong [V2DI V4SI])
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;; Vec float modes
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;; Vec float modes
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(define_mode_iterator VF [V4SF])
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(define_mode_iterator VF [V4SF])
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;; Vec modes, pity mode iterators are not composable
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;; Vec modes, pity mode iterators are not composable
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@ -1627,6 +1631,25 @@
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"vrl<VI_char> %0,%1,%2"
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"vrl<VI_char> %0,%1,%2"
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[(set_attr "type" "vecsimple")])
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[(set_attr "type" "vecsimple")])
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(define_insn "altivec_vrl<VI_char>mi"
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[(set (match_operand:VIlong 0 "register_operand" "=v")
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(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "0")
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(match_operand:VIlong 2 "register_operand" "v")
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(match_operand:VIlong 3 "register_operand" "v")]
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UNSPEC_VRLMI))]
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"TARGET_P9_VECTOR"
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"vrl<VI_char>mi %0,%2,%3"
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[(set_attr "type" "veclogical")])
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(define_insn "altivec_vrl<VI_char>nm"
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[(set (match_operand:VIlong 0 "register_operand" "=v")
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(unspec:VIlong [(match_operand:VIlong 1 "register_operand" "v")
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(match_operand:VIlong 2 "register_operand" "v")]
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UNSPEC_VRLNM))]
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"TARGET_P9_VECTOR"
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"vrl<VI_char>nm %0,%1,%2"
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[(set_attr "type" "veclogical")])
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(define_insn "altivec_vsl"
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(define_insn "altivec_vsl"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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@ -1927,12 +1927,22 @@ BU_P9V_OVERLOAD_2 (VSRV, "vsrv")
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BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3)
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BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3)
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BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3)
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BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3)
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BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3)
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BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3)
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BU_P9V_AV_2 (VRLWNM, "vrlwnm", CONST, altivec_vrlwnm)
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BU_P9V_AV_2 (VRLDNM, "vrldnm", CONST, altivec_vrldnm)
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/* ISA 3.0 vector overloaded 2 argument functions. */
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/* ISA 3.0 vector overloaded 2 argument functions. */
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BU_P9V_OVERLOAD_2 (VADU, "vadu")
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BU_P9V_OVERLOAD_2 (VADU, "vadu")
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BU_P9V_OVERLOAD_2 (VADUB, "vadub")
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BU_P9V_OVERLOAD_2 (VADUB, "vadub")
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BU_P9V_OVERLOAD_2 (VADUH, "vaduh")
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BU_P9V_OVERLOAD_2 (VADUH, "vaduh")
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BU_P9V_OVERLOAD_2 (VADUW, "vaduw")
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BU_P9V_OVERLOAD_2 (VADUW, "vaduw")
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BU_P9V_OVERLOAD_2 (RLNM, "rlnm")
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/* ISA 3.0 3-argument vector functions. */
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BU_P9V_AV_3 (VRLWMI, "vrlwmi", CONST, altivec_vrlwmi)
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BU_P9V_AV_3 (VRLDMI, "vrldmi", CONST, altivec_vrldmi)
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/* ISA 3.0 vector overloaded 3-argument functions. */
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BU_P9V_OVERLOAD_3 (RLMI, "rlmi")
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/* 1 argument vsx scalar functions added in ISA 3.0 (power9). */
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/* 1 argument vsx scalar functions added in ISA 3.0 (power9). */
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BU_P9V_64BIT_VSX_1 (VSEEDP, "scalar_extract_exp", CONST, xsxexpdp)
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BU_P9V_64BIT_VSX_1 (VSEEDP, "scalar_extract_exp", CONST, xsxexpdp)
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@ -2214,6 +2214,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
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{ ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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{ P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
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{ P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
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{ P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
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RS6000_BTI_unsigned_V4SI, 0 },
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{ P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
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RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
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{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
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{ ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
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@ -18187,6 +18187,43 @@ If any of the enabled test conditions is true, the corresponding entry
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in the result vector is -1. Otherwise (all of the enabled test
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in the result vector is -1. Otherwise (all of the enabled test
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conditions are false), the corresponding entry of the result vector is 0.
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conditions are false), the corresponding entry of the result vector is 0.
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The following built-in functions are available for the PowerPC family
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of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
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@smallexample
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vector unsigned int vec_rlmi (vector unsigned int, vector unsigned int,
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vector unsigned int);
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vector unsigned long long vec_rlmi (vector unsigned long long,
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vector unsigned long long,
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vector unsigned long long);
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vector unsigned int vec_rlnm (vector unsigned int, vector unsigned int,
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vector unsigned int);
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vector unsigned long long vec_rlnm (vector unsigned long long,
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vector unsigned long long,
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vector unsigned long long);
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vector unsigned int vec_vrlnm (vector unsigned int, vector unsigned int);
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vector unsigned long long vec_vrlnm (vector unsigned long long,
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vector unsigned long long);
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@end smallexample
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The result of @code{vec_rlmi} is obtained by rotating each element of
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the first argument vector left and inserting it under mask into the
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second argument vector. The third argument vector contains the mask
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beginning in bits 11:15, the mask end in bits 19:23, and the shift
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count in bits 27:31, of each element.
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The result of @code{vec_rlnm} is obtained by rotating each element of
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the first argument vector left and ANDing it with a mask specified by
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the second and third argument vectors. The second argument vector
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contains the shift count for each element in the low-order byte. The
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third argument vector contains the mask end for each element in the
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low-order byte, with the mask begin in the next higher byte.
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The result of @code{vec_vrlnm} is obtained by rotating each element
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of the first argument vector left and ANDing it with a mask. The
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second argument vector contains the mask beginning in bits 11:15,
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the mask end in bits 19:23, and the shift count in bits 27:31,
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of each element.
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If the cryptographic instructions are enabled (@option{-mcrypto} or
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If the cryptographic instructions are enabled (@option{-mcrypto} or
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@option{-mcpu=power8}), the following builtins are enabled.
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@option{-mcpu=power8}), the following builtins are enabled.
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@ -1,3 +1,7 @@
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2017-01-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* vec-rlmi-rlnm.c: New file.
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2017-01-17 Nathan Sidwell <nathan@acm.org>
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2017-01-17 Nathan Sidwell <nathan@acm.org>
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PR c++/61636
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PR c++/61636
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@ -0,0 +1,69 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target lp64 } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-O2 -mcpu=power9" } */
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#include <altivec.h>
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vector unsigned int
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rlmi_test_1 (vector unsigned int x, vector unsigned int y,
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vector unsigned int z)
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{
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return vec_rlmi (x, y, z);
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}
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vector unsigned long long
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rlmi_test_2 (vector unsigned long long x, vector unsigned long long y,
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vector unsigned long long z)
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{
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return vec_rlmi (x, y, z);
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}
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vector unsigned int
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vrlnm_test_1 (vector unsigned int x, vector unsigned int y)
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{
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return vec_vrlnm (x, y);
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}
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vector unsigned long long
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vrlnm_test_2 (vector unsigned long long x, vector unsigned long long y)
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{
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return vec_vrlnm (x, y);
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}
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vector unsigned int
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rlnm_test_1 (vector unsigned int x, vector unsigned int y,
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vector unsigned int z)
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{
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return vec_rlnm (x, y, z);
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}
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vector unsigned long long
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rlnm_test_2 (vector unsigned long long x, vector unsigned long long y,
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vector unsigned long long z)
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{
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return vec_rlnm (x, y, z);
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}
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/* Expected code generation for rlmi_test_1 is vrlwmi.
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Expected code generation for rlmi_test_2 is vrldmi.
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Expected code generation for vrlnm_test_1 is vrlwnm.
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Expected code generation for vrlnm_test_2 is vrldnm.
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Expected code generation for the others is more complex, because
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the second and third arguments are combined by a shift and OR,
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and because there is no splat-immediate doubleword.
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- For rlnm_test_1: vspltisw, vslw, xxlor, vrlwnm.
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- For rlnm_test_2: xxspltib, vextsb2d, vsld, xxlor, vrldnm.
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There is a choice of splat instructions in both cases, so we
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just check for "splt". */
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/* { dg-final { scan-assembler-times "vrlwmi" 1 } } */
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/* { dg-final { scan-assembler-times "vrldmi" 1 } } */
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/* { dg-final { scan-assembler-times "splt" 2 } } */
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/* { dg-final { scan-assembler-times "vextsb2d" 1 } } */
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/* { dg-final { scan-assembler-times "vslw" 1 } } */
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/* { dg-final { scan-assembler-times "vsld" 1 } } */
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/* { dg-final { scan-assembler-times "xxlor" 2 } } */
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/* { dg-final { scan-assembler-times "vrlwnm" 2 } } */
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/* { dg-final { scan-assembler-times "vrldnm" 2 } } */
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