re PR target/24914 (gcc fails when built with --with-cpu=ep9312 --with-fpu=maverick)
PR target/24914 * arm.c (arm_hard_regno_mode_ok): Co-processor registers aren't ok when not generating code to use that co-processor. From-SVN: r107187
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@ -1,3 +1,9 @@
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2005-11-18 Richard Earnshaw <richard.earnshaw@arm.com>
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PR target/24914
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* arm.c (arm_hard_regno_mode_ok): Co-processor registers aren't ok
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when not generating code to use that co-processor.
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2005-11-18 James A. Morrison <phython@gcc.gnu.org>
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* tree-flow.h (reserve_phi_args_for_new_edge, create_phi_node,
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@ -11818,7 +11818,9 @@ int
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arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
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{
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if (GET_MODE_CLASS (mode) == MODE_CC)
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return regno == CC_REGNUM || regno == VFPCC_REGNUM;
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return (regno == CC_REGNUM
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|| (TARGET_HARD_FLOAT && TARGET_VFP
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&& regno == VFPCC_REGNUM));
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if (TARGET_THUMB)
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/* For the Thumb we only allow values bigger than SImode in
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@ -11828,7 +11830,8 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
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start of an even numbered register pair. */
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return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
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if (IS_CIRRUS_REGNUM (regno))
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if (TARGET_HARD_FLOAT && TARGET_MAVERICK
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&& IS_CIRRUS_REGNUM (regno))
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/* We have outlawed SI values in Cirrus registers because they
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reside in the lower 32 bits, but SF values reside in the
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upper 32 bits. This causes gcc all sorts of grief. We can't
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@ -11836,7 +11839,8 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
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get sign extended to 64bits-- aldyh. */
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return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
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if (IS_VFP_REGNUM (regno))
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if (TARGET_HARD_FLOAT && TARGET_VFP
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&& IS_VFP_REGNUM (regno))
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{
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if (mode == SFmode || mode == SImode)
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return TRUE;
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@ -11847,28 +11851,32 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
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return FALSE;
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}
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if (IS_IWMMXT_GR_REGNUM (regno))
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return mode == SImode;
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if (IS_IWMMXT_REGNUM (regno))
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return VALID_IWMMXT_REG_MODE (mode);
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if (TARGET_REALLY_IWMMXT)
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{
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if (IS_IWMMXT_GR_REGNUM (regno))
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return mode == SImode;
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if (IS_IWMMXT_REGNUM (regno))
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return VALID_IWMMXT_REG_MODE (mode);
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}
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/* We allow any value to be stored in the general registers.
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Restrict doubleword quantities to even register pairs so that we can
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use ldrd. */
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if (regno <= LAST_ARM_REGNUM)
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return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
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if ( regno == FRAME_POINTER_REGNUM
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if (regno == FRAME_POINTER_REGNUM
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|| regno == ARG_POINTER_REGNUM)
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/* We only allow integers in the fake hard registers. */
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return GET_MODE_CLASS (mode) == MODE_INT;
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/* The only registers left are the FPA registers
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which we only allow to hold FP values. */
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return GET_MODE_CLASS (mode) == MODE_FLOAT
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&& regno >= FIRST_FPA_REGNUM
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&& regno <= LAST_FPA_REGNUM;
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return (TARGET_HARD_FLOAT && TARGET_FPA
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&& GET_MODE_CLASS (mode) == MODE_FLOAT
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&& regno >= FIRST_FPA_REGNUM
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&& regno <= LAST_FPA_REGNUM);
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}
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int
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