* config/ns32k/ns32k.h (target_flags, MASK_32081, MASK_RTD)
(MASK_REGPARM, MASK_32532, MASK_32332, MASK_NO_SB, MASK_NO_BITFIELD) (MASK_HIMEM, MASK_32381, MASK_MULT_ADD, MASK_SRC, MASK_IEEE_COMPARE) (TARGET_32081, TARGET_32381, TARGET_MULT_ADD, TARGET_RTD) (TARGET_REGPARM, TARGET_32532, TARGET_32332, TARGET_SB, TARGET_HIMEM) (TARGET_BITFIELD, TARGET_IEEE_COMPARE, TARGET_SWITCHES): Delete. (OVERRIDE_OPTIONS): Clear MASK_SB instead of setting MASK_NO_SB. * config/ns32k/netbsd.h (TARGET_DEFAULT): Remove MASK_NO_SB and MASK_NO_BITFIELD. * config/ns32k/ns32k.c (ns32k_handle_option): New function. (TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults. * config/ns32k/ns32k.opt: New file. From-SVN: r98018
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
4af06170d8
commit
a6d1d98047
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@ -1,3 +1,18 @@
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2005-04-12 Richard Sandiford <rsandifo@redhat.com>
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* config/ns32k/ns32k.h (target_flags, MASK_32081, MASK_RTD)
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(MASK_REGPARM, MASK_32532, MASK_32332, MASK_NO_SB, MASK_NO_BITFIELD)
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(MASK_HIMEM, MASK_32381, MASK_MULT_ADD, MASK_SRC, MASK_IEEE_COMPARE)
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(TARGET_32081, TARGET_32381, TARGET_MULT_ADD, TARGET_RTD)
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(TARGET_REGPARM, TARGET_32532, TARGET_32332, TARGET_SB, TARGET_HIMEM)
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(TARGET_BITFIELD, TARGET_IEEE_COMPARE, TARGET_SWITCHES): Delete.
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(OVERRIDE_OPTIONS): Clear MASK_SB instead of setting MASK_NO_SB.
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* config/ns32k/netbsd.h (TARGET_DEFAULT): Remove MASK_NO_SB and
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MASK_NO_BITFIELD.
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* config/ns32k/ns32k.c (ns32k_handle_option): New function.
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(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
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* config/ns32k/ns32k.opt: New file.
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2005-04-12 Richard Sandiford <rsandifo@redhat.com>
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* config.gcc (m68k-*-linux*): Add m68k/ieee.opt to $extra_options.
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@ -36,8 +36,7 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
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MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
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(MASK_32532 | MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
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/* 32-bit alignment for efficiency */
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@ -64,6 +64,7 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
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static const char *const ns32k_out_reg_names[] = OUTPUT_REGISTER_NAMES;
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static bool ns32k_handle_option (size_t, const char *, int);
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static rtx gen_indexed_expr (rtx, rtx, rtx);
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static const char *singlemove_string (rtx *);
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static void move_tail (rtx[], int, int);
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@ -94,6 +95,11 @@ static int ns32k_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
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#undef TARGET_ASM_FUNCTION_EPILOGUE
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#define TARGET_ASM_FUNCTION_EPILOGUE ns32k_output_function_epilogue
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#undef TARGET_DEFAULT_TARGET_FLAGS
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#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
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#undef TARGET_HANDLE_OPTION
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#define TARGET_HANDLE_OPTION ns32k_handle_option
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#undef TARGET_RTX_COSTS
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#define TARGET_RTX_COSTS ns32k_rtx_costs
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#undef TARGET_ADDRESS_COST
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@ -110,6 +116,35 @@ static int ns32k_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Implement TARGET_HANDLE_OPTION. */
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static bool
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ns32k_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
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int value ATTRIBUTE_UNUSED)
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{
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switch (code)
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{
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case OPT_m32081:
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target_flags &= ~MASK_32381;
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return true;
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case OPT_msoft_float:
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target_flags &= ~(MASK_32081 | MASK_32381);
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return true;
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case OPT_m32332:
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target_flags &= ~MASK_32532;
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return true;
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case OPT_m32032:
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target_flags &= ~(MASK_32332 | MASK_32532);
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return true;
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default:
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return true;
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}
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}
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/* Generate the assembly code for function entry. FILE is a stdio
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stream to output the code to. SIZE is an int: how many units of
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temporary storage to allocate.
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@ -78,99 +78,6 @@ Boston, MA 02111-1307, USA. */
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#define PUT_EXTERNAL_PREFIX(FILE)
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#endif
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/* Run-time compilation parameters selecting different hardware subsets. */
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extern int target_flags;
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/* Masks for target_flags */
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#define MASK_32081 1
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#define MASK_RTD 2
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#define MASK_REGPARM 4
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#define MASK_32532 8
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#define MASK_32332 16
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#define MASK_NO_SB 32
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#define MASK_NO_BITFIELD 64
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#define MASK_HIMEM 128
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#define MASK_32381 256
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#define MASK_MULT_ADD 512
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#define MASK_SRC 1024
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#define MASK_IEEE_COMPARE 2048
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/* Macros used in the machine description to test the flags. */
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/* Compile 32081 insns for floating point (not library calls). */
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#define TARGET_32081 (target_flags & MASK_32081)
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#define TARGET_32381 (target_flags & MASK_32381)
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/* The use of multiply-add instructions is optional because there may
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* be cases where it produces worse code.
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*/
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#define TARGET_MULT_ADD (target_flags & MASK_MULT_ADD)
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/* Compile using rtd insn calling sequence.
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This will not work unless you use prototypes at least
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for all functions that can take varying numbers of args. */
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#define TARGET_RTD (target_flags & MASK_RTD)
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/* Compile passing first two args in regs 0 and 1. */
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#define TARGET_REGPARM (target_flags & MASK_REGPARM)
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/* Options to select type of CPU, for better optimization.
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The output is correct for any kind of 32000 regardless of these options. */
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#define TARGET_32532 (target_flags & MASK_32532)
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#define TARGET_32332 (target_flags & MASK_32332)
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/* Ok to use the static base register (and presume it's 0) */
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#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
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#define TARGET_HIMEM (target_flags & MASK_HIMEM)
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/* Compile using bit-field insns. */
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#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
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#define TARGET_IEEE_COMPARE (target_flags & MASK_IEEE_COMPARE)
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/* Macro to define tables used to set the flags.
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This is a list in braces of pairs in braces,
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each pair being { "NAME", VALUE }
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where VALUE is the bits to set or minus the bits to clear.
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An empty string NAME is used to identify the default VALUE. */
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#define TARGET_SWITCHES \
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{ { "32081", MASK_32081, N_("Use hardware fp")}, \
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{ "soft-float", -(MASK_32081|MASK_32381), \
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N_("Don't use hardware fp")}, \
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{ "rtd", MASK_RTD, N_("Alternative calling convention")}, \
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{ "nortd", -MASK_RTD, N_("Use normal calling convention")}, \
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{ "regparm", MASK_REGPARM, N_("Pass some arguments in registers")}, \
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{ "noregparm", -MASK_REGPARM, N_("Pass all arguments on stack")}, \
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{ "32532", MASK_32532|MASK_32332, N_("Optimize for 32532 cpu")}, \
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{ "32332", MASK_32332, N_("Optimize for 32332 cpu")}, \
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{ "32332", -MASK_32532, 0}, \
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{ "32032", -(MASK_32532|MASK_32332), N_("Optimize for 32032")}, \
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{ "sb", -MASK_NO_SB, \
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N_("Register sb is zero. Use for absolute addressing")}, \
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{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
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{ "bitfield", -MASK_NO_BITFIELD, \
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N_("Use bit-field instructions")}, \
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{ "nobitfield", MASK_NO_BITFIELD, \
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N_("Do not use bit-field instructions")}, \
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{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
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{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
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{ "32381", MASK_32381, N_("32381 fpu")}, \
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{ "mult-add", MASK_MULT_ADD, \
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N_("Use multiply-accumulate fp instructions")}, \
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{ "nomult-add", -MASK_MULT_ADD, \
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N_("Do not use multiply-accumulate fp instructions") }, \
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{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
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{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
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{ "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")}, \
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{ "noieee-compare", -MASK_IEEE_COMPARE, \
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N_("Do not use IEEE math for fp comparisons")}, \
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{ "", TARGET_DEFAULT, 0}}
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/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
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/* When we are generating PIC, the sb is used as a pointer
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to the GOT. 32381 is a superset of 32081 */
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@ -179,7 +86,7 @@ extern int target_flags;
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if (target_flags & MASK_32532) \
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target_flags |= MASK_32332; \
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if (flag_pic || TARGET_HIMEM) \
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target_flags |= MASK_NO_SB; \
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target_flags &= ~MASK_SB; \
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if (TARGET_32381) \
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target_flags |= MASK_32081; \
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else \
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@ -0,0 +1,108 @@
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; Options for the NS32000 port of the compiler.
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; Copyright (C) 2005 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 2, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING. If not, write to the Free
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; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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; 02111-1307, USA.
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m32032
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Target RejectNegative
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Optimize for 32032
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m32081
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Target RejectNegative Report Mask(32081)
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Use hardware fp
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m32332
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Target RejectNegative Report Mask(32332)
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Optimize for 32332
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m32381
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Target RejectNegative Report Mask(32381)
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Use the 32381 fpu
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m32532
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Target RejectNegative Report Mask(32532)
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Optimize for 32532
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mbitfield
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Target RejectNegative Report Mask(BITFIELD)
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Use bit-field instructions
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mhimem
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Target RejectNegative Report Mask(HIMEM)
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Generate code for high memory
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mieee-compare
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Target RejectNegative Report Mask(IEEE_COMPARE)
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Use IEEE math for fp comparisons
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mmult-add
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Target RejectNegative Report Mask(MULT_ADD)
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Use multiply-accumulate fp instructions
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mnobitfield
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Target RejectNegative Report InverseMask(BITFIELD)
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Do not use bit-field instructions
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mnohimem
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Target RejectNegative Report InverseMask(HIMEM)
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Generate code for low memory
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mnoieee-compare
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Target RejectNegative Report InverseMask(IEEE_COMPARE)
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Do not use IEEE math for fp comparisons
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mnomult-add
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Target RejectNegative Report InverseMask(MULT_ADD)
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Do not use multiply-accumulate fp instructions
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mnoregparm
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Target RejectNegative Report InverseMask(REGPARM)
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Pass all arguments on the stack
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mnortd
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Target RejectNegative Report InverseMask(RTD)
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Use the normal calling convention
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mnosb
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Target RejectNegative Report InverseMask(SB)
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Do not use register sb
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mnosrc
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Target RejectNegative Report InverseMask(SRC)
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Do not use the 'small register classes' kludge
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mregparm
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Target RejectNegative Report Mask(REGPARM)
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Pass some arguments in registers
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mrtd
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Target RejectNegative Report Mask(RTD)
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Use an alternative calling convention
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msb
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Target RejectNegative Report Mask(SB)
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Register sb is zero, use it for absolute addressing
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msoft-float
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Target RejectNegative
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Do not use hardware fp
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msrc
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Target RejectNegative Report Mask(SRC)
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Use the 'small register classes' kludge
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