ia64.c (ia64_load_pair_ok): New.
gcc/ 2005-07-28 Jan Beulich <jbeulich@novell.com> * config/ia64/ia64.c (ia64_load_pair_ok): New. (ia64_print_operand): Describe and handle 'X'. (ia64_register_move_cost): Also handle FP_REGS. (ia64_preferred_reload_class): Likewise. (ia64_secondary_reload_class): Likewise. (ia64_dependencies_evaluation_hook): New local variable c. Initialize it. Also check for ITANIUM_CLASS_FLDP. * config/ia64/ia64.h (FP_REGNO_P): New. (HARD_REGNO_MODE_OK): Remove explusion of TImode. (reg_class): Add FP_REGS. (REG_CLASS_NAMES): Adjust for it. (REG_CLASS_CONTENTS): Likewise. (REGNO_REG_CLASS): Use FP_REGS where appropriate. (REG_CLASS_FROM_LETTER): Handle 'x'. (CLASS_MAX_NREGS): Handle FP_REGS. (MEMORY_MOVE_COST): Likewise. * config/ia64/ia64.md (itanium_class): Add fldp. (type): Handle fldp. (movti_internal): More allowable operand combinations. Use ldfp8 when splitting unnecessary. Remove predicable attribute. Adjust itanium_class attribute. (smuldi3_highpart): Remove outdated comment. (mulditi3, umulditi3, rotlti3): New expanders. (addti3, subti3, mulditi3_internal, umulditi3_internal, negti2, rotlti3_internal): New insns. (absti2): Disabled new insn for future reference. Respective new splitters. * config/ia64/itanium1.md (1_fldp, 1b_fldp): New insn reservations. * config/ia64/itanium2.md (2_fldp, 2b_fldp): Likewise. * config/ia64/ia64-protos.h (ia64_load_pair_ok): New. From-SVN: r102463
This commit is contained in:
Jan Beulich
Jan Beulich
parent
9e7705cbd1
commit
a71aef0bb3
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@ -1,3 +1,35 @@
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2005-07-28 Jan Beulich <jbeulich@novell.com>
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* config/ia64/ia64.c (ia64_load_pair_ok): New.
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(ia64_print_operand): Describe and handle 'X'.
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(ia64_register_move_cost): Also handle FP_REGS.
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(ia64_preferred_reload_class): Likewise.
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(ia64_secondary_reload_class): Likewise.
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(ia64_dependencies_evaluation_hook): New local variable c. Initialize
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it. Also check for ITANIUM_CLASS_FLDP.
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* config/ia64/ia64.h (FP_REGNO_P): New.
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(HARD_REGNO_MODE_OK): Remove explusion of TImode.
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(reg_class): Add FP_REGS.
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(REG_CLASS_NAMES): Adjust for it.
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(REG_CLASS_CONTENTS): Likewise.
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(REGNO_REG_CLASS): Use FP_REGS where appropriate.
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(REG_CLASS_FROM_LETTER): Handle 'x'.
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(CLASS_MAX_NREGS): Handle FP_REGS.
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(MEMORY_MOVE_COST): Likewise.
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* config/ia64/ia64.md (itanium_class): Add fldp.
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(type): Handle fldp.
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(movti_internal): More allowable operand combinations. Use ldfp8 when
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splitting unnecessary. Remove predicable attribute. Adjust
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itanium_class attribute.
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(smuldi3_highpart): Remove outdated comment.
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(mulditi3, umulditi3, rotlti3): New expanders.
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(addti3, subti3, mulditi3_internal, umulditi3_internal, negti2, rotlti3_internal): New insns.
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(absti2): Disabled new insn for future reference.
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Respective new splitters.
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* config/ia64/itanium1.md (1_fldp, 1b_fldp): New insn reservations.
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* config/ia64/itanium2.md (2_fldp, 2b_fldp): Likewise.
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* config/ia64/ia64-protos.h (ia64_load_pair_ok): New.
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2005-07-25 James A. Morrison <phython@gcc.gnu.org>
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PR rtl-optimization/23047
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@ -41,6 +41,7 @@ extern bool ia64_legitimate_constant_p (rtx);
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extern rtx ia64_expand_move (rtx, rtx);
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extern int ia64_move_ok (rtx, rtx);
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extern int ia64_load_pair_ok (rtx, rtx);
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extern int addp4_optimize_ok (rtx, rtx);
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extern void ia64_emit_cond_move (rtx, rtx, rtx);
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extern int ia64_depz_field_mask (rtx, rtx);
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@ -690,6 +690,37 @@ ia64_move_ok (rtx dst, rtx src)
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return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
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}
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/* Return 1 if the operands are ok for a floating point load pair. */
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int
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ia64_load_pair_ok (rtx dst, rtx src)
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{
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if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
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return 0;
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if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
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return 0;
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switch (GET_CODE (XEXP (src, 0)))
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{
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case REG:
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case POST_INC:
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break;
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case POST_DEC:
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return 0;
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case POST_MODIFY:
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{
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rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
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if (GET_CODE (adjust) != CONST_INT
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|| INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
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return 0;
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}
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break;
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default:
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abort ();
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}
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return 1;
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}
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int
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addp4_optimize_ok (rtx op1, rtx op2)
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{
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@ -4305,6 +4336,7 @@ ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
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for Intel assembler.
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U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
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for Intel assembler.
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X A pair of floating point registers.
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r Print register name, or constant 0 as r0. HP compatibility for
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Linux kernel.
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v Print vector constant value as an 8-byte integer value. */
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@ -4453,6 +4485,13 @@ ia64_print_operand (FILE * file, rtx x, int code)
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}
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break;
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case 'X':
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{
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unsigned int regno = REGNO (x);
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fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
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}
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return;
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case 'r':
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/* If this operand is the constant zero, write it as register zero.
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Any register, zero, or CONST_INT value is OK here. */
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@ -4682,6 +4721,7 @@ ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
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case GR_REGS:
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case FR_REGS:
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case FP_REGS:
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case GR_AND_FR_REGS:
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case GR_AND_BR_REGS:
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case ALL_REGS:
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@ -4703,6 +4743,7 @@ ia64_preferred_reload_class (rtx x, enum reg_class class)
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switch (class)
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{
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case FR_REGS:
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case FP_REGS:
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/* Don't allow volatile mem reloads into floating point registers.
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This is defined to force reload to choose the r/m case instead
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of the f/f case when reloading (set (reg fX) (mem/v)). */
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@ -4768,6 +4809,7 @@ ia64_secondary_reload_class (enum reg_class class,
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break;
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case FR_REGS:
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case FP_REGS:
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/* Need to go through general registers to get to other class regs. */
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if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
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return GR_REGS;
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@ -6113,16 +6155,19 @@ ia64_dependencies_evaluation_hook (rtx head, rtx tail)
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{
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for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
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{
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enum attr_itanium_class c;
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if (REG_NOTE_KIND (link) != REG_DEP_TRUE)
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continue;
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next = XEXP (link, 0);
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if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
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|| ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
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c = ia64_safe_itanium_class (next);
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if ((c == ITANIUM_CLASS_ST
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|| c == ITANIUM_CLASS_STF)
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&& ia64_st_address_bypass_p (insn, next))
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break;
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else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
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|| ia64_safe_itanium_class (next)
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== ITANIUM_CLASS_FLD)
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else if ((c == ITANIUM_CLASS_LD
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|| c == ITANIUM_CLASS_FLD
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|| c == ITANIUM_CLASS_FLDP)
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&& ia64_ld_address_bypass_p (insn, next))
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break;
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}
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@ -324,6 +324,7 @@ while (0)
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#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
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#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
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#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
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#define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
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#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
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#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
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#define GENERAL_REGNO_P(REGNO) \
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@ -651,7 +652,6 @@ while (0)
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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(FR_REGNO_P (REGNO) ? \
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GET_MODE_CLASS (MODE) != MODE_CC && \
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(MODE) != TImode && \
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(MODE) != BImode && \
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(MODE) != TFmode \
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: PR_REGNO_P (REGNO) ? \
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@ -721,6 +721,7 @@ enum reg_class
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AR_I_REGS,
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ADDL_REGS,
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GR_REGS,
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FP_REGS,
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FR_REGS,
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GR_AND_BR_REGS,
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GR_AND_FR_REGS,
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@ -737,7 +738,7 @@ enum reg_class
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constants. These names are used in writing some of the debugging dumps. */
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
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"ADDL_REGS", "GR_REGS", "FR_REGS", \
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"ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
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"GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
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/* An initializer containing the contents of the register classes, as integers
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@ -774,6 +775,10 @@ enum reg_class
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x0100 }, \
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/* FP_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, \
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0x00000000, 0x00000000, 0x0000 }, \
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/* FR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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@ -801,7 +806,8 @@ enum reg_class
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#define REGNO_REG_CLASS(REGNO) \
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(ADDL_REGNO_P (REGNO) ? ADDL_REGS \
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: GENERAL_REGNO_P (REGNO) ? GR_REGS \
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: FR_REGNO_P (REGNO) ? FR_REGS \
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: FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
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&& (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
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: PR_REGNO_P (REGNO) ? PR_REGS \
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: BR_REGNO_P (REGNO) ? BR_REGS \
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: AR_M_REGNO_P (REGNO) ? AR_M_REGS \
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@ -832,6 +838,7 @@ enum reg_class
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: (CHAR) == 'c' ? PR_REGS \
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: (CHAR) == 'd' ? AR_M_REGS \
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: (CHAR) == 'e' ? AR_I_REGS \
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: (CHAR) == 'x' ? FP_REGS \
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: NO_REGS)
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/* A C expression which is nonzero if register number NUM is suitable for use
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@ -888,8 +895,8 @@ enum reg_class
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
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: ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
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: ((CLASS) == FR_REGS && (MODE) == XCmode) ? 2 \
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: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
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: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
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: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* In FP regs, we can't change FP values to integer values and vice versa,
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@ -1414,7 +1421,7 @@ do { \
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/* A C expression for the cost of moving data of mode M between a
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register and memory. */
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#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
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((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
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((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS || (CLASS) == FP_REGS \
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|| (CLASS) == GR_AND_FR_REGS ? 4 : 10)
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/* A C expression for the cost of a branch instruction. A value of 1 is the
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@ -123,15 +123,15 @@
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;; which emit instruction that can go in any slot (e.g. nop).
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(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
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fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
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chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
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fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
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ld,chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
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st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
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nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
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(const_string "unknown"))
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;; chk_s has an I and an M form; use type A for convenience.
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(define_attr "type" "unknown,A,I,M,F,B,L,X,S"
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(cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
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(cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
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(eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
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(eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
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(eq_attr "itanium_class" "lfetch") (const_string "M")
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@ -659,18 +659,22 @@
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})
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(define_insn_and_split "*movti_internal"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:TI 1 "general_operand" "ri,m,r"))]
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r, *fm,*x,*f, Q")
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(match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
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"ia64_move_ok (operands[0], operands[1])"
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"#"
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"reload_completed"
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"@
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#
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#
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ldfp8 %X0 = %1%P1
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#
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#"
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"reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
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[(const_int 0)]
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{
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ia64_split_tmode_move (operands);
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DONE;
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}
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[(set_attr "itanium_class" "unknown")
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(set_attr "predicable" "no")])
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[(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
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;; Floating Point Moves
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;;
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@ -2140,9 +2144,6 @@
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(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
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"")
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;; ??? There are highpart multiply and add instructions, but we have no way
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;; to generate them.
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(define_insn "smuldi3_highpart"
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[(set (match_operand:DI 0 "fr_register_operand" "=f")
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(truncate:DI
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|
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@ -2493,6 +2494,200 @@
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;; ::::::::::::::::::::
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;; ::
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;; :: 128 bit Integer arithmetic
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;; ::
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;; ::::::::::::::::::::
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(define_insn "addti3"
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[(set (match_operand:TI 0 "gr_register_operand" "=&r")
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(plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
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(match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
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(clobber (match_scratch:BI 3 "=&c"))]
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""
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"#"
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[(set_attr "itanium_class" "unknown")])
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(define_split
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[(set (match_operand:TI 0 "register_operand" "")
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(plus:TI (match_operand:TI 1 "register_operand" "")
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(match_operand:TI 2 "register_operand" "")))
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(clobber (match_scratch:BI 3 ""))]
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"reload_completed"
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[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
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(cond_exec (eq (match_dup 3) (const_int 0))
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(set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
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(cond_exec (ne (match_dup 3) (const_int 0))
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(set (match_dup 4)
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(plus:DI (plus:DI (match_dup 5) (match_dup 6))
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(const_int 1))))]
|
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{
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operands[4] = gen_highpart (DImode, operands[0]);
|
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operands[0] = gen_lowpart (DImode, operands[0]);
|
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operands[5] = gen_highpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, operands[1]);
|
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operands[6] = gen_highpart (DImode, operands[2]);
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operands[2] = gen_lowpart (DImode, operands[2]);
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})
|
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|
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(define_split
|
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[(set (match_operand:TI 0 "register_operand" "")
|
||||
(plus:TI (match_operand:TI 1 "register_operand" "")
|
||||
(match_operand:TI 2 "immediate_operand" "")))
|
||||
(clobber (match_scratch:BI 3 ""))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
|
||||
(cond_exec (eq (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4)
|
||||
(plus:DI (match_dup 5) (match_dup 6))))
|
||||
(cond_exec (ne (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4)
|
||||
(plus:DI (match_dup 5) (match_dup 7))))]
|
||||
{
|
||||
operands[4] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
operands[5] = gen_highpart (DImode, operands[1]);
|
||||
operands[1] = gen_lowpart (DImode, operands[1]);
|
||||
operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
|
||||
operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
|
||||
})
|
||||
|
||||
(define_insn "subti3"
|
||||
[(set (match_operand:TI 0 "gr_register_operand" "=&r")
|
||||
(minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
|
||||
(match_operand:TI 2 "gr_register_operand" "r")))
|
||||
(clobber (match_scratch:BI 3 "=&c"))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "itanium_class" "unknown")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:TI 0 "register_operand" "")
|
||||
(minus:TI (match_operand:TI 1 "register_operand" "")
|
||||
(match_operand:TI 2 "register_operand" "")))
|
||||
(clobber (match_scratch:BI 3 "=&c"))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
|
||||
(cond_exec (eq (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
|
||||
(cond_exec (ne (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4)
|
||||
(plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
|
||||
{
|
||||
operands[4] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
operands[5] = gen_highpart (DImode, operands[1]);
|
||||
operands[1] = gen_lowpart (DImode, operands[1]);
|
||||
operands[6] = gen_highpart (DImode, operands[2]);
|
||||
operands[2] = gen_lowpart (DImode, operands[2]);
|
||||
})
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:TI 0 "register_operand" "")
|
||||
(minus:TI (match_operand:TI 1 "immediate_operand" "")
|
||||
(match_operand:TI 2 "register_operand" "")))
|
||||
(clobber (match_scratch:BI 3 "=&c"))]
|
||||
"reload_completed && CONST_OK_FOR_K (INTVAL (operands[1]))"
|
||||
[(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
|
||||
(cond_exec (ne (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
|
||||
(cond_exec (eq (match_dup 3) (const_int 0))
|
||||
(set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
|
||||
{
|
||||
operands[4] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
operands[5] = gen_highpart (DImode, operands[2]);
|
||||
operands[2] = gen_lowpart (DImode, operands[2]);
|
||||
operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
|
||||
operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
|
||||
})
|
||||
|
||||
(define_expand "mulditi3"
|
||||
[(set (match_operand:TI 0 "fr_register_operand" "")
|
||||
(mult:TI (sign_extend:TI
|
||||
(match_operand:DI 1 "fr_register_operand" ""))
|
||||
(sign_extend:TI
|
||||
(match_operand:DI 2 "fr_register_operand" ""))))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*mulditi3_internal"
|
||||
[(set (match_operand:TI 0 "fr_register_operand" "=&f")
|
||||
(mult:TI (sign_extend:TI
|
||||
(match_operand:DI 1 "fr_register_operand" "%f"))
|
||||
(sign_extend:TI
|
||||
(match_operand:DI 2 "fr_register_operand" "f"))))]
|
||||
""
|
||||
"#"
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3) (truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (sign_extend:TI (match_dup 1))
|
||||
(sign_extend:TI (match_dup 2)))
|
||||
(const_int 64))))]
|
||||
{
|
||||
operands[3] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
}
|
||||
[(set_attr "itanium_class" "unknown")])
|
||||
|
||||
(define_expand "umulditi3"
|
||||
[(set (match_operand:TI 0 "fr_register_operand" "")
|
||||
(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "fr_register_operand" ""))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "fr_register_operand" ""))))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*umulditi3_internal"
|
||||
[(set (match_operand:TI 0 "fr_register_operand" "=&f")
|
||||
(mult:TI (zero_extend:TI
|
||||
(match_operand:DI 1 "fr_register_operand" "%f"))
|
||||
(zero_extend:TI
|
||||
(match_operand:DI 2 "fr_register_operand" "f"))))]
|
||||
""
|
||||
"#"
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 3) (truncate:DI
|
||||
(lshiftrt:TI
|
||||
(mult:TI (zero_extend:TI (match_dup 1))
|
||||
(zero_extend:TI (match_dup 2)))
|
||||
(const_int 64))))]
|
||||
{
|
||||
operands[3] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
}
|
||||
[(set_attr "itanium_class" "unknown")])
|
||||
|
||||
(define_insn_and_split "negti2"
|
||||
[(set (match_operand:TI 0 "gr_register_operand" "=&r")
|
||||
(neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
|
||||
(clobber (match_scratch:BI 2 "=&c"))]
|
||||
""
|
||||
"#"
|
||||
"reload_completed"
|
||||
[(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
|
||||
(set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
|
||||
(cond_exec (eq (match_dup 2) (const_int 0))
|
||||
(set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
|
||||
(cond_exec (ne (match_dup 2) (const_int 0))
|
||||
(set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
|
||||
{
|
||||
operands[3] = gen_highpart (DImode, operands[0]);
|
||||
operands[0] = gen_lowpart (DImode, operands[0]);
|
||||
operands[4] = gen_highpart (DImode, operands[1]);
|
||||
operands[1] = gen_lowpart (DImode, operands[1]);
|
||||
}
|
||||
[(set_attr "itanium_class" "unknown")])
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 32 bit floating point arithmetic
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
|
@ -4505,6 +4700,54 @@
|
|||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "rotlti3"
|
||||
[(set (match_operand:TI 0 "gr_register_operand" "")
|
||||
(rotate:TI (match_operand:TI 1 "gr_register_operand" "")
|
||||
(match_operand:DI 2 "nonmemory_operand" "")))]
|
||||
""
|
||||
{
|
||||
if (! dshift_count_operand (operands[2], DImode))
|
||||
FAIL;
|
||||
})
|
||||
|
||||
(define_insn_and_split "*rotlti3_internal"
|
||||
[(set (match_operand:TI 0 "gr_register_operand" "=&r")
|
||||
(rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
|
||||
(match_operand:DI 2 "dshift_count_operand" "n")))]
|
||||
""
|
||||
"#"
|
||||
"reload_completed"
|
||||
[(const_int 0)]
|
||||
{
|
||||
HOST_WIDE_INT count = INTVAL (operands[2]);
|
||||
rtx rl = gen_lowpart (DImode, operands[0]);
|
||||
rtx rh = gen_highpart (DImode, operands[0]);
|
||||
rtx lo = gen_lowpart (DImode, operands[1]);
|
||||
rtx hi = gen_highpart (DImode, operands[1]);
|
||||
rtx countlo = GEN_INT (-count & 63);
|
||||
|
||||
if (count & 64)
|
||||
{
|
||||
if (count & 63)
|
||||
{
|
||||
emit_insn (gen_shrp (rl, hi, lo, countlo));
|
||||
emit_insn (gen_shrp (rh, lo, hi, countlo));
|
||||
}
|
||||
else
|
||||
{
|
||||
emit_move_insn (rl, hi);
|
||||
emit_move_insn (rh, lo);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
emit_insn (gen_shrp (rl, lo, hi, countlo));
|
||||
emit_insn (gen_shrp (rh, hi, lo, countlo));
|
||||
}
|
||||
DONE;
|
||||
}
|
||||
[(set_attr "itanium_class" "unknown")])
|
||||
|
||||
(define_insn "shrp"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "=r")
|
||||
(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
|
||||
|
|
|
|||
|
|
@ -529,6 +529,10 @@
|
|||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fld"))
|
||||
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
|
||||
(define_insn_reservation "1_fldp" 9
|
||||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fldp"))
|
||||
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
|
||||
(define_insn_reservation "1_fmac" 5
|
||||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fmac"))
|
||||
|
|
@ -1407,6 +1411,10 @@
|
|||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fld"))
|
||||
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
|
||||
(define_insn_reservation "1b_fldp" 9
|
||||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fldp"))
|
||||
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
|
||||
(define_insn_reservation "1b_fmac" 5
|
||||
(and (and (eq_attr "cpu" "itanium")
|
||||
(eq_attr "itanium_class" "fmac"))
|
||||
|
|
|
|||
|
|
@ -734,6 +734,11 @@
|
|||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fld"))
|
||||
(eq (symbol_ref "bundling_p") (const_int 0))) "2_M")
|
||||
(define_insn_reservation "2_fldp" 6
|
||||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fldp"))
|
||||
(eq (symbol_ref "bundling_p") (const_int 0)))
|
||||
"2_M_only_um01")
|
||||
(define_insn_reservation "2_fmac" 4
|
||||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fmac"))
|
||||
|
|
@ -1541,6 +1546,11 @@
|
|||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fld"))
|
||||
(ne (symbol_ref "bundling_p") (const_int 0))) "2b_M")
|
||||
(define_insn_reservation "2b_fldp" 6
|
||||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fldp"))
|
||||
(ne (symbol_ref "bundling_p") (const_int 0)))
|
||||
"2b_M_only_um01")
|
||||
(define_insn_reservation "2b_fmac" 4
|
||||
(and (and (eq_attr "cpu" "itanium2")
|
||||
(eq_attr "itanium_class" "fmac"))
|
||||
|
|
|
|||
Loading…
Reference in New Issue