Fix Thumb2 bic orn
2009-05-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.md (*arm_iorsi3): Refactored for only ARM.
(peephole ior (reg, int) -> mov, ior): Refactored for only ARM.
* config/arm/thumb2.md (*thumb_andsi_not_shiftsi_si): Allow bic
with shifts for Thumb2.
(orsi_notsi): New for orn.
(*thumb_orsi_notshiftsi_si): Allow orn with shifts.
(*thumb2_iorsi3): Rewrite support for iorsi for Thumb2.
* config/arm/arm.c (const_ok_for_op): Split case for IOR for
Thumb2.
(arm_gen_constant): Set can_invert for IOR and Thumb2, Add
comments. Don't invert remainder for IOR.
From-SVN: r147729
This commit is contained in:
Ramana Radhakrishnan
Ramana Radhakrishnan
parent
875d0f10a6
commit
a7994a57b9
@ -1,3 +1,17 @@
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2009-05-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config/arm/arm.md (*arm_iorsi3): Refactored for only ARM.
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(peephole ior (reg, int) -> mov, ior): Refactored for only ARM.
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* config/arm/thumb2.md (*thumb_andsi_not_shiftsi_si): Allow bic
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with shifts for Thumb2.
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(orsi_notsi): New for orn.
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(*thumb_orsi_notshiftsi_si): Allow orn with shifts.
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(*thumb2_iorsi3): Rewrite support for iorsi for Thumb2.
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* config/arm/arm.c (const_ok_for_op): Split case for IOR for
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Thumb2.
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(arm_gen_constant): Set can_invert for IOR and Thumb2, Add
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comments. Don't invert remainder for IOR.
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2009-05-19 Zdenek Dvorak <ook@ucw.cz>
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PR tree-optimization/40087
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@ -2008,7 +2008,11 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
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case MINUS: /* Should only occur with (MINUS I reg) => rsb */
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case XOR:
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return 0;
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case IOR:
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if (TARGET_THUMB2)
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return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
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return 0;
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case AND:
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@ -2185,15 +2189,20 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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GEN_INT (ARM_SIGN_EXTEND (val))));
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return 1;
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}
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if (remainder == 0)
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{
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if (reload_completed && rtx_equal_p (target, source))
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return 0;
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if (generate)
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emit_constant_insn (cond,
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gen_rtx_SET (VOIDmode, target, source));
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return 1;
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}
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if (TARGET_THUMB2)
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can_invert = 1;
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break;
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case AND:
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@ -2281,6 +2290,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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/* Calculate a few attributes that may be useful for specific
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optimizations. */
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/* Count number of leading zeros. */
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for (i = 31; i >= 0; i--)
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{
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if ((remainder & (1 << i)) == 0)
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@ -2289,6 +2299,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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break;
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}
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/* Count number of leading 1's. */
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for (i = 31; i >= 0; i--)
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{
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if ((remainder & (1 << i)) != 0)
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@ -2297,6 +2308,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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break;
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}
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/* Count number of trailing zero's. */
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for (i = 0; i <= 31; i++)
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{
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if ((remainder & (1 << i)) == 0)
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@ -2305,6 +2317,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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break;
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}
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/* Count number of trailing 1's. */
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for (i = 0; i <= 31; i++)
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{
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if ((remainder & (1 << i)) != 0)
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@ -2492,6 +2505,17 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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if (code == XOR)
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break;
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/* Convert.
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x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
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and the remainder 0s for e.g. 0xfff00000)
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x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
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This can be done in 2 instructions by using shifts with mov or mvn.
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e.g. for
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x = x | 0xfff00000;
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we generate.
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mvn r0, r0, asl #12
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mvn r0, r0, lsr #12 */
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if (set_sign_bit_copies > 8
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&& (val & (-1 << (32 - set_sign_bit_copies))) == val)
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{
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@ -2517,6 +2541,16 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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return 2;
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}
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/* Convert
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x = y | constant (which has set_zero_bit_copies number of trailing ones).
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to
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x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
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For eg. r0 = r0 | 0xfff
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mvn r0, r0, lsr #12
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mvn r0, r0, asl #12
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*/
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if (set_zero_bit_copies > 8
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&& (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
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{
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@ -2542,6 +2576,13 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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return 2;
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}
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/* This will never be reached for Thumb2 because orn is a valid
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instruction. This is for Thumb1 and the ARM 32 bit cases.
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x = y | constant (such that ~constant is a valid constant)
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Transform this to
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x = ~(~y & ~constant).
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*/
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if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
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{
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if (generate)
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@ -2651,7 +2692,8 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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if (remainder & (1 << i))
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num_bits_set++;
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if (code == AND || (can_invert && num_bits_set > 16))
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if ((code == AND)
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|| (code != IOR && can_invert && num_bits_set > 16))
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remainder = (~remainder) & 0xffffffff;
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else if (code == PLUS && num_bits_set > 16)
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remainder = (-remainder) & 0xffffffff;
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@ -2615,11 +2615,11 @@
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(ior:SI (match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
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"TARGET_32BIT"
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"TARGET_ARM"
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"@
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orr%?\\t%0, %1, %2
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#"
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"TARGET_32BIT
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"TARGET_ARM
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&& GET_CODE (operands[2]) == CONST_INT
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&& !const_ok_for_arm (INTVAL (operands[2]))"
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[(clobber (const_int 0))]
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@ -2646,7 +2646,7 @@
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(set (match_operand:SI 0 "arm_general_register_operand" "")
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(ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
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(match_operand:SI 2 "const_int_operand" "")))]
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"TARGET_32BIT
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"TARGET_ARM
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&& !const_ok_for_arm (INTVAL (operands[2]))
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&& const_ok_for_arm (~INTVAL (operands[2]))"
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[(set (match_dup 3) (match_dup 2))
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@ -57,7 +57,7 @@
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[(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 3 "const_int_operand" "M")]))
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(match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_ARM"
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"TARGET_THUMB2"
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"bic%?\\t%0, %1, %2%S4"
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[(set_attr "predicable" "yes")
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(set_attr "shift" "2")
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@ -1252,3 +1252,47 @@
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(set_attr "length" "2")]
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)
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(define_insn "orsi_notsi_si"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
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(match_operand:SI 1 "reg_or_int_operand" "rK")))]
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"TARGET_THUMB2"
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"orn%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")]
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)
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(define_insn "*thumb_orsi_not_shiftsi_si"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(ior:SI (not:SI (match_operator:SI 4 "shift_operator"
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[(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 3 "const_int_operand" "M")]))
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(match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_THUMB2"
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"orn%?\\t%0, %1, %2%S4"
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[(set_attr "predicable" "yes")
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(set_attr "shift" "2")
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(set_attr "type" "alu_shift")]
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)
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(define_insn_and_split "*thumb2_iorsi3"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
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(ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
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(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
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"TARGET_THUMB2"
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"@
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orr%?\\t%0, %1, %2
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orn%?\\t%0, %1, #%B2
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#"
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"TARGET_THUMB2
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&& GET_CODE (operands[2]) == CONST_INT
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&& !(const_ok_for_arm (INTVAL (operands[2]))
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|| const_ok_for_arm (~INTVAL (operands[2])))"
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[(clobber (const_int 0))]
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"
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arm_split_constant (IOR, SImode, curr_insn,
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INTVAL (operands[2]), operands[0], operands[1], 0);
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DONE;
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"
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[(set_attr "length" "4,4,16")
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(set_attr "predicable" "yes")]
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)
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