From a7b376eeb6b470b23a739038f57f0f2846fde1fb Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Tue, 20 Feb 2007 02:26:06 +0000 Subject: [PATCH] c4x.md, [...]: Follow spelling conventions. * config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c, config/fr30/fr30.md, config/i386/i386.h, config/iq2000/iq2000.h, config/iq2000/predicates.md, config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h, config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h, config/pdp11/pdp11.c, config/pdp11/pdp11.h, config/rs6000/altivec.md, config/rs6000/rs6000.c, config/s390/s390-modes.def, config/sparc/netbsd-elf.h, config/sparc/sparc.c, config/sparc/sparc.h, config/sparc/sparc.md, config/spu/constraints.md, config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling conventions. From-SVN: r122151 --- gcc/ChangeLog | 13 +++++++++++++ gcc/config/c4x/c4x.md | 4 ++-- gcc/config/cris/cris.c | 2 +- gcc/config/crx/crx.c | 12 ++++++------ gcc/config/fr30/fr30.md | 20 ++++++++++---------- gcc/config/i386/i386.h | 2 +- gcc/config/iq2000/iq2000.h | 6 +++--- gcc/config/iq2000/predicates.md | 6 +++--- gcc/config/pa/milli64.S | 4 ++-- gcc/config/pa/pa.c | 2 +- gcc/config/pa/pa.h | 8 ++++---- gcc/config/pa/pa.md | 2 +- gcc/config/pa/pa32-regs.h | 2 +- gcc/config/pa/pa64-regs.h | 2 +- gcc/config/pdp11/pdp11.c | 2 +- gcc/config/pdp11/pdp11.h | 8 ++++---- gcc/config/rs6000/altivec.md | 2 +- gcc/config/rs6000/rs6000.c | 20 ++++++++++---------- gcc/config/s390/s390-modes.def | 2 +- gcc/config/sparc/netbsd-elf.h | 2 +- gcc/config/sparc/sparc.c | 2 +- gcc/config/sparc/sparc.h | 4 ++-- gcc/config/sparc/sparc.md | 8 ++++---- gcc/config/spu/constraints.md | 22 +++++++++++----------- gcc/config/spu/spu.c | 10 +++++----- gcc/config/stormy16/stormy16.md | 20 ++++++++++---------- 26 files changed, 100 insertions(+), 87 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2861d3f7215..4af0ac01346 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -6,6 +6,19 @@ config/arc/arc.h, config/arm/arm.c, config/arm/arm.md, config/arm/lib1funcs.asm: Follow spelling conventions. + * config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c, + config/fr30/fr30.md, config/i386/i386.h, + config/iq2000/iq2000.h, config/iq2000/predicates.md, + config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h, + config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h, + config/pdp11/pdp11.c, config/pdp11/pdp11.h, + config/rs6000/altivec.md, config/rs6000/rs6000.c, + config/s390/s390-modes.def, config/sparc/netbsd-elf.h, + config/sparc/sparc.c, config/sparc/sparc.h, + config/sparc/sparc.md, config/spu/constraints.md, + config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling + conventions. + 2007-02-20 Alan Modra PR target/29943 diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 5054383e520..1d2833f3a33 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -29,7 +29,7 @@ ; for QImode and Pmode, whether Pmode was QImode or PQImode. ; For addresses we wouldn't have to have a clobber of the CC ; associated with each insn and we could use MPYI in address -; calculations without having to synthesize a proper 32 bit multiply. +; calculations without having to synthesize a proper 32-bit multiply. ; Additional C30/C40 instructions not coded: ; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond @@ -123,7 +123,7 @@ ; L unsigned 16-bit ; M unsigned 8-bit (C4x only) ; N ones complement of unsigned 16-bit -; O 16 bit high constant +; O 16-bit high constant ; Q ARx + 9-bit signed disp ; R ARx + 5-bit unsigned disp (C4x only) ; S ARx + 0, 1, IRx disp diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index ad97764226b..2158295f9a4 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -1632,7 +1632,7 @@ cris_rtx_costs (rtx x, int code, int outer_code, int *total) /* Eight or 16 bits are a word and cycle more expensive. */ else if (val <= 32767 && val >= -32768) *total = 2; - /* A 32 bit constant (or very seldom, unsigned 16 bits) costs + /* A 32-bit constant (or very seldom, unsigned 16 bits) costs another word. FIXME: This isn't linear to 16 bits. */ else *total = 4; diff --git a/gcc/config/crx/crx.c b/gcc/config/crx/crx.c index 838993e8174..7b8efee42b0 100644 --- a/gcc/config/crx/crx.c +++ b/gcc/config/crx/crx.c @@ -546,12 +546,12 @@ crx_function_arg_regno_p (int n) * The following addressing modes are supported on CRX: * * Relocations --> const | symbol_ref | label_ref - * Absolute address --> 32 bit absolute - * Post increment --> reg + 12 bit disp. - * Post modify --> reg + 12 bit disp. - * Register relative --> reg | 32 bit disp. + reg | 4 bit + reg - * Scaled index --> reg + reg | 22 bit disp. + reg + reg | - * 22 disp. + reg + reg + (2 | 4 | 8) */ + * Absolute address --> 32-bit absolute + * Post increment --> reg + 12-bit disp. + * Post modify --> reg + 12-bit disp. + * Register relative --> reg | 32-bit disp. + reg | 4 bit + reg + * Scaled index --> reg + reg | 22-bit disp. + reg + reg | + * 22-disp. + reg + reg + (2 | 4 | 8) */ static int crx_addr_reg_p (rtx addr_reg) { diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index c40a7097d60..4e8e93acfa2 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -746,7 +746,7 @@ ;;}}} ;;{{{ Multiplication -;; Signed multiplication producing 64 bit results from 32 bit inputs +;; Signed multiplication producing 64-bit results from 32-bit inputs (define_insn "mulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -757,7 +757,7 @@ [(set_attr "length" "6")] ) -;; Unsigned multiplication producing 64 bit results from 32 bit inputs +;; Unsigned multiplication producing 64-bit results from 32-bit inputs (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -768,7 +768,7 @@ [(set_attr "length" "6")] ) -;; Signed multiplication producing 32 bit result from 16 bit inputs +;; Signed multiplication producing 32-bit result from 16-bit inputs (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -779,7 +779,7 @@ [(set_attr "length" "4")] ) -;; Unsigned multiplication producing 32 bit result from 16 bit inputs +;; Unsigned multiplication producing 32-bit result from 16-bit inputs (define_insn "umulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -790,7 +790,7 @@ [(set_attr "length" "4")] ) -;; Signed multiplication producing 32 bit result from 32 bit inputs +;; Signed multiplication producing 32-bit result from 32-bit inputs (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%r") @@ -884,7 +884,7 @@ ;;}}} ;;{{{ Logical Operations -;; Logical AND, 32 bit integers +;; Logical AND, 32-bit integers (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operand:SI 1 "register_operand" "%r") @@ -894,7 +894,7 @@ "and %1, %0" ) -;; Inclusive OR, 32 bit integers +;; Inclusive OR, 32-bit integers (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -904,7 +904,7 @@ "or %1, %0" ) -;; Exclusive OR, 32 bit integers +;; Exclusive OR, 32-bit integers (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "%r") @@ -914,7 +914,7 @@ "eor %1, %0" ) -;; One's complement, 32 bit integers +;; One's complement, 32-bit integers (define_expand "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "") (not:SI (match_operand:SI 1 "register_operand" "")))] @@ -1152,7 +1152,7 @@ ;; far away the destination is. ;; The calculation for the instruction length is derived as follows: -;; The branch instruction has a 9 bit signed displacement so we have +;; The branch instruction has a 9-bit signed displacement so we have ;; this inequality for the displacement: ;; ;; -256 <= pc < 256 diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 1664a8fb403..4dab579130d 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1955,7 +1955,7 @@ do { \ /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ -/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". +/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". For non floating point regs, the following are the HImode names. For float regs, the stack top is sometimes referred to as "%st(0)" diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index 45c1c349a08..24ea3e0ba1d 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -252,12 +252,12 @@ enum reg_class /* For IQ2000: `I' is used for the range of constants an arithmetic insn can - actually contain (16 bits signed integers). + actually contain (16-bits signed integers). `J' is used for the range which is just zero (i.e., $r0). `K' is used for the range of constants a logical insn can actually - contain (16 bit zero-extended integers). + contain (16-bit zero-extended integers). `L' is used for the range of constants that be loaded with lui (i.e., the bottom 16 bits are zero). @@ -267,7 +267,7 @@ enum reg_class `N' is used for constants 0xffffnnnn or 0xnnnnffff - `O' is a 5 bit zero-extended integer. */ + `O' is a 5-bit zero-extended integer. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \ diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md index 7f797a3cf60..996d0ce8b34 100644 --- a/gcc/config/iq2000/predicates.md +++ b/gcc/config/iq2000/predicates.md @@ -18,7 +18,7 @@ ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ;; Boston, MA 02110-1301, USA. -;; Return 1 if OP can be used as an operand where a register or 16 bit +;; Return 1 if OP can be used as an operand where a register or 16-bit ;; unsigned integer is needed. (define_predicate "uns_arith_operand" @@ -30,7 +30,7 @@ return register_operand (op, mode); }) -;; Return 1 if OP can be used as an operand where a 16 bit integer is +;; Return 1 if OP can be used as an operand where a 16-bit integer is ;; needed. (define_predicate "arith_operand" @@ -50,7 +50,7 @@ return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); }) -;; Return 1 if OP is a 32 bit integer which is too big to be loaded +;; Return 1 if OP is a 32-bit integer which is too big to be loaded ;; with one instruction. (define_predicate "large_int" diff --git a/gcc/config/pa/milli64.S b/gcc/config/pa/milli64.S index eb8fed105e0..ffcafa30a6d 100644 --- a/gcc/config/pa/milli64.S +++ b/gcc/config/pa/milli64.S @@ -411,7 +411,7 @@ LSYM(small_divisor) #if defined(pa64) /* Clear the upper 32 bits of the arg1 register. We are working with */ -/* small divisors (and 32 bit integers) We must not be mislead */ +/* small divisors (and 32-bit integers) We must not be mislead */ /* by "1" bits left in the upper 32 bits. */ depd %r0,31,32,%r25 #endif @@ -626,7 +626,7 @@ LSYM(special_divisor) #if defined(pa64) /* Clear the upper 32 bits of the arg1 register. We are working with - small divisors (and 32 bit unsigned integers) We must not be mislead + small divisors (and 32-bit unsigned integers) We must not be mislead by "1" bits left in the upper 32 bits. */ depd %r0,31,32,%r25 #endif diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index b63239808f7..e39ddc79a32 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -576,7 +576,7 @@ adddi3_operand (rtx op, enum machine_mode mode) } /* True iff zdepi can be used to generate this CONST_INT. - zdepi first sign extends a 5 bit signed number to a given field + zdepi first sign extends a 5-bit signed number to a given field length, then places this field anywhere in a zero. */ int zdepi_cint_p (unsigned HOST_WIDE_INT x) diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 853de9871fd..60a72459581 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -487,10 +487,10 @@ extern struct rtx_def *hppa_pic_save_rtx (void); C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. - `I' is used for the 11 bit constants. - `J' is used for the 14 bit constants. + `I' is used for the 11-bit constants. + `J' is used for the 14-bit constants. `K' is used for values that can be moved with a zdepi insn. - `L' is used for the 5 bit constants. + `L' is used for the 5-bit constants. `M' is used for 0. `N' is used for values with the least significant 11 bits equal to zero and when sign extended from 32 to 64 bits the @@ -1321,7 +1321,7 @@ extern int may_call_alloca; function's constant-pool, because such addresses can actually be output as REG+SMALLINT. - Note we only allow 5 bit immediates for access to a constant address; + Note we only allow 5-bit immediates for access to a constant address; doing so avoids losing for loading/storing a FP register at an address which will not fit in 5 bits. */ diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 61dbb46992e..d686cb82b57 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -4638,7 +4638,7 @@ "!TARGET_64BIT" "* { - /* Don't output a 64 bit constant, since we can't trust the assembler to + /* Don't output a 64-bit constant, since we can't trust the assembler to handle it correctly. */ if (GET_CODE (operands[2]) == CONST_DOUBLE) operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2])); diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index a17c117726a..fa0f0f9c36e 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -15,7 +15,7 @@ HP-PA 1.1 has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable - as 32 bit registers. So, we will set things up like the 68k which + as 32-bit registers. So, we will set things up like the 68k which has different fp units: define separate register sets for the 1.0 and 1.1 fp units. */ diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index cbf2d981c6c..e356407f8fd 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -31,7 +31,7 @@ Boston, MA 02110-1301, USA. */ HP-PA 2.0w has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable - as 32 bit registers. + as 32-bit registers. Due to limitations within GCC itself, we do not expose the left/right half addressability when in wide mode. This is not a major performance diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 3e295b174b6..92320593d99 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -584,7 +584,7 @@ output_move_double (rtx *operands) operands[1] = GEN_INT (INTVAL(operands[1]) & 0xff); } else - /* immediate 32 bit values not allowed */ + /* immediate 32-bit values not allowed */ gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE); } else diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index a8e8d4d58bf..a018914db4b 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -97,7 +97,7 @@ Boston, MA 02110-1301, USA. */ #define UNITS_PER_WORD 2 /* This machine doesn't use IEEE floats. */ -/* Because the pdp11 (at least Unix) convention for 32 bit ints is +/* Because the pdp11 (at least Unix) convention for 32-bit ints is big endian, opposite for what you need for float, the vax float conversion routines aren't actually used directly. But the underlying format is indeed the vax/pdp11 float format. */ @@ -286,10 +286,10 @@ extern const struct real_format pdp11_d_format; /* The pdp has a couple of classes: -MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication - (even numbered do 32 bit multiply) +MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication + (even numbered do 32-bit multiply) LMUL_REGS long multiply registers (even numbered regs ) - (don't need them, all 32 bit regs are even numbered!) + (don't need them, all 32-bit regs are even numbered!) GENERAL_REGS is all cpu LOAD_FPU_REGS is the first four cpu regs, they are easier to load NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index c10615e7315..006fcfbe369 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -587,7 +587,7 @@ DONE; }") -;; 32 bit integer multiplication +;; 32-bit integer multiplication ;; A_high = Operand_0 & 0xFFFF0000 >> 16 ;; A_low = Operand_0 & 0xFFFF ;; B_high = Operand_1 & 0xFFFF0000 >> 16 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3835a9a5928..ecedffd8fec 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3530,7 +3530,7 @@ rs6000_legitimize_tls_address (rtx addr, enum tls_model model) } else { - /* IE, or 64 bit offset LE. */ + /* IE, or 64-bit offset LE. */ tmp2 = gen_reg_rtx (Pmode); if (TARGET_64BIT) insn = gen_tls_got_tprel_64 (tmp2, got, addr); @@ -9271,22 +9271,22 @@ rs6000_common_init_builtins (void) && mode3 == V4SImode) type = v4sf_ftype_v4sf_v4sf_v4si; - /* vchar, vchar, vchar, 4 bit literal. */ + /* vchar, vchar, vchar, 4-bit literal. */ else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 && mode3 == QImode) type = v16qi_ftype_v16qi_v16qi_int; - /* vshort, vshort, vshort, 4 bit literal. */ + /* vshort, vshort, vshort, 4-bit literal. */ else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 && mode3 == QImode) type = v8hi_ftype_v8hi_v8hi_int; - /* vint, vint, vint, 4 bit literal. */ + /* vint, vint, vint, 4-bit literal. */ else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 && mode3 == QImode) type = v4si_ftype_v4si_v4si_int; - /* vfloat, vfloat, vfloat, 4 bit literal. */ + /* vfloat, vfloat, vfloat, 4-bit literal. */ else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 && mode3 == QImode) type = v4sf_ftype_v4sf_v4sf_int; @@ -9390,23 +9390,23 @@ rs6000_common_init_builtins (void) else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) type = v4si_ftype_v8hi_v4si; - /* vint, vint, 5 bit literal. */ + /* vint, vint, 5-bit literal. */ else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) type = v4si_ftype_v4si_int; - /* vshort, vshort, 5 bit literal. */ + /* vshort, vshort, 5-bit literal. */ else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) type = v8hi_ftype_v8hi_int; - /* vchar, vchar, 5 bit literal. */ + /* vchar, vchar, 5-bit literal. */ else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) type = v16qi_ftype_v16qi_int; - /* vfloat, vint, 5 bit literal. */ + /* vfloat, vint, 5-bit literal. */ else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) type = v4sf_ftype_v4si_int; - /* vint, vfloat, 5 bit literal. */ + /* vint, vfloat, 5-bit literal. */ else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) type = v4si_ftype_v4sf_int; diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def index afcfb1b69e6..fcc2657cf03 100644 --- a/gcc/config/s390/s390-modes.def +++ b/gcc/config/s390/s390-modes.def @@ -119,7 +119,7 @@ information necessary for CCT1 and CCT2 modes.): CCSR, CCUR -There are several instructions comparing 32 bit with 64 bit unsigned/signed +There are several instructions comparing 32 bit with 64-bit unsigned/signed values. Such instructions can be considered to have a builtin zero/sign_extend. The problem is that in the RTL (to be canonical) the zero/sign extended operand has to be the first one but the machine instructions like it the other way diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h index b07fee3bc81..55300522310 100644 --- a/gcc/config/sparc/netbsd-elf.h +++ b/gcc/config/sparc/netbsd-elf.h @@ -85,7 +85,7 @@ Boston, MA 02110-1301, USA. */ #define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME); /* Below here exists the merged NetBSD/sparc & NetBSD/sparc64 compiler - description, allowing one to build 32 bit or 64 bit applications + description, allowing one to build 32-bit or 64-bit applications on either. We define the sparc & sparc64 versions of things, occasionally a neutral version (should be the same as "netbsd-elf.h") and then based on SPARC_BI_ARCH, DEFAULT_ARCH32_P, and TARGET_CPU_DEFAULT, diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 45bc9e187e5..764beb946ea 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -3493,7 +3493,7 @@ mem_min_alignment (rtx mem, int desired) hard register number, and one indexed by mode. */ /* The purpose of sparc_mode_class is to shrink the range of modes so that - they all fit (as bit numbers) in a 32 bit word (again). Each real mode is + they all fit (as bit numbers) in a 32-bit word (again). Each real mode is mapped into one sparc_mode_class mode. */ enum sparc_mode_class { diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 936fac861cf..db0e34e516d 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -500,7 +500,7 @@ extern enum cmodel sparc_cmodel; /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y to get high 32 bits. False in V8+ or V9 because multiply stores - a 64 bit result in a register. */ + a 64-bit result in a register. */ #define TARGET_HARD_MUL32 \ ((TARGET_V8 || TARGET_SPARCLITE \ @@ -708,7 +708,7 @@ if (TARGET_ARCH64 \ even those that are not normally considered general registers. SPARC has 32 integer registers and 32 floating point registers. - 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not + 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not accessible. We still account for them to simplify register computations (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 32+32+32+4 == 100. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index ed68f1e8a1e..387b3405db5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1237,7 +1237,7 @@ "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG && (GET_MODE (operands[1]) == CCXmode - /* 32 bit LTU/GEU are better implemented using addx/subx. */ + /* 32-bit LTU/GEU are better implemented using addx/subx. */ || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) @@ -4592,7 +4592,7 @@ ;; Integer multiply/divide instructions. -;; The 32 bit multiply/divide instructions are deprecated on v9, but at +;; The 32-bit multiply/divide instructions are deprecated on v9, but at ;; least in UltraSPARC I, II and IIi it is a win tick-wise. (define_insn "mulsi3" @@ -4699,8 +4699,8 @@ } }) -;; V9 puts the 64 bit product in a 64 bit register. Only out or global -;; registers can hold 64 bit values in the V8plus environment. +;; V9 puts the 64-bit product in a 64-bit register. Only out or global +;; registers can hold 64-bit values in the V8plus environment. ;; XXX (define_insn "mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md index 45aafd0350d..abc319b4ff5 100644 --- a/gcc/config/spu/constraints.md +++ b/gcc/config/spu/constraints.md @@ -25,23 +25,23 @@ ;; another treats it as 64 bit, and the third sign extends it to 128 bit. (define_constraint "A" - "An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value." + "An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32-bit value." (ior (and (match_code "const_int,const_double,const_vector") (match_test "immediate_load_p (op, SImode)")) (match_code "symbol_ref,label_ref,high,const"))) (define_constraint "B" - "An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32 bit value." + "An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "arith_immediate_p (op, SImode, -0x200, 0x1ff)"))) (define_constraint "C" - "An immediate for and/xor/or instructions. const_int is treated as a 32 bit value." + "An immediate for and/xor/or instructions. const_int is treated as a 32-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "logical_immediate_p (op, SImode)"))) (define_constraint "D" - "An immediate for iohl instruction. const_int is treated as a 32 bit value." + "An immediate for iohl instruction. const_int is treated as a 32-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "iohl_immediate_p (op, SImode)"))) @@ -51,7 +51,7 @@ (match_test "immediate_load_p (op, TImode)"))) (define_constraint "W" - "An immediate for shift and rotate instructions. const_int is treated as a 32 bit value." + "An immediate for shift and rotate instructions. const_int is treated as a 32-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "arith_immediate_p (op, SImode, -0x40, 0x3f)"))) @@ -66,17 +66,17 @@ (match_test "iohl_immediate_p (op, TImode)"))) (define_constraint "a" - "An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value." + "An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64-bit value." (and (match_code "const_int") (match_test "immediate_load_p (op, DImode)"))) (define_constraint "c" - "An immediate for and/xor/or instructions. const_int is treated as a 64 bit value." + "An immediate for and/xor/or instructions. const_int is treated as a 64-bit value." (and (match_code "const_int") (match_test "logical_immediate_p (op, DImode)"))) (define_constraint "d" - "An immediate for iohl instruction. const_int is treated as a 64 bit value." + "An immediate for iohl instruction. const_int is treated as a 64-bit value." (and (match_code "const_int") (match_test "iohl_immediate_p (op, DImode)"))) @@ -86,12 +86,12 @@ (match_test "fsmbi_const_p (op)"))) (define_constraint "j" - "An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32 bit value." + "An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "cpat_const_p (op, SImode)"))) (define_constraint "k" - "An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64 bit value." + "An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64-bit value." (and (match_code "const_int,const_double,const_vector") (match_test "cpat_const_p (op, DImode)"))) @@ -119,7 +119,7 @@ (match_test "ival >= -0x200 && ival <= 0x1ff"))) (define_constraint "M" - "A signed 16 bit immediate for @code{stop}." + "A signed 16-bit immediate for @code{stop}." (and (match_code "const_int") (match_test "ival >= -0x8000ll && ival <= 0x7fffll"))) diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 5297a7b9550..9adeacf2088 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -1969,7 +1969,7 @@ insert_branch_hints (void) because they are only at the end of a block and are considered when we are deciding whether to propagate - we're getting too far away from the branch. The hbr insns - only have a signed 10 bit offset + only have a signed 10-bit offset We go back as far as possible so the branch will be considered for propagation when we get to the beginning of the block. */ next = 0; @@ -2280,7 +2280,7 @@ legitimate_const (rtx x, int aligned) { /* We can never know if the resulting address fits in 18 bits and can be loaded with ila. Instead we should use the HI and LO relocations to - load a 32 bit address. */ + load a 32-bit address. */ rtx sym, cst; gcc_assert (GET_CODE (x) == CONST); @@ -2588,11 +2588,11 @@ arith_immediate_p (rtx op, enum machine_mode mode, } /* We accept: - - any 32 bit constant (SImode, SFmode) + - any 32-bit constant (SImode, SFmode) - any constant that can be generated with fsmbi (any mode) - - a 64 bit constant where the high and low bits are identical + - a 64-bit constant where the high and low bits are identical (DImode, DFmode) - - a 128 bit constant where the four 32 bit words match. */ + - a 128-bit constant where the four 32-bit words match. */ int spu_legitimate_constant_p (rtx x) { diff --git a/gcc/config/stormy16/stormy16.md b/gcc/config/stormy16/stormy16.md index 5ffb14746d3..3a85345f1d7 100644 --- a/gcc/config/stormy16/stormy16.md +++ b/gcc/config/stormy16/stormy16.md @@ -300,7 +300,7 @@ ;; :::::::::::::::::::: ;; :: -;; :: 16 bit Integer arithmetic +;; :: 16-bit Integer arithmetic ;; :: ;; :::::::::::::::::::: @@ -449,7 +449,7 @@ "mul" [(set_attr "psw_operand" "nop")]) -;; Unsigned multiplication producing 64 bit results from 32 bit inputs +;; Unsigned multiplication producing 64-bit results from 32-bit inputs ; The constraint on operand 0 is 't' because it is actually two regs ; long, and both regs must match the constraint. (define_insn "umulhisi3" @@ -522,7 +522,7 @@ ;; :::::::::::::::::::: ;; :: -;; :: 16 bit Integer Shifts and Rotates +;; :: 16-bit Integer Shifts and Rotates ;; :: ;; :::::::::::::::::::: @@ -556,11 +556,11 @@ ;; :::::::::::::::::::: ;; :: -;; :: 16 Bit Integer Logical operations +;; :: 16-Bit Integer Logical operations ;; :: ;; :::::::::::::::::::: -;; Logical AND, 16 bit integers +;; Logical AND, 16-bit integers (define_insn "andhi3" [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W") (and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0") @@ -590,7 +590,7 @@ } ") -;; Inclusive OR, 16 bit integers +;; Inclusive OR, 16-bit integers (define_insn "iorhi3" [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W") (ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0") @@ -620,7 +620,7 @@ } ") -;; Exclusive OR, 16 bit integers +;; Exclusive OR, 16-bit integers (define_insn "xorhi3" [(set (match_operand:HI 0 "register_operand" "=T,r,r") (xor:HI (match_operand:HI 1 "register_operand" "%0,0,0") @@ -632,7 +632,7 @@ xor %0,%2" [(set_attr "length" "2,2,4")]) -;; One's complement, 16 bit integers +;; One's complement, 16-bit integers (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "register_operand" "=r") (not:HI (match_operand:HI 1 "register_operand" "0")))] @@ -642,7 +642,7 @@ ;; :::::::::::::::::::: ;; :: -;; :: 32 bit Integer arithmetic +;; :: 32-bit Integer arithmetic ;; :: ;; :::::::::::::::::::: @@ -695,7 +695,7 @@ ;; :::::::::::::::::::: ;; :: -;; :: 32 bit Integer Shifts and Rotates +;; :: 32-bit Integer Shifts and Rotates ;; :: ;; ::::::::::::::::::::