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alpha.md (umk_mismatch_args): Don't put a mode on set. 

* config/alpha/alpha.md (umk_mismatch_args): Don't put a mode on set.
	* config/fr30/fr30.md: Likweise
	(movsi_push): Likewise.
	(movsi_pop): Likewise.
	(enter_func): Likewise.
	* config/moxie/moxie.md (movsi_push): Likewise.
	(movsi_pop): Likewise.

From-SVN: r168817
This commit is contained in:
Mike Stump 2011-01-14 19:37:16 +00:00 committed by Mike Stump
parent ed4ebabc90
commit a7edae0a63
5 changed files with 104 additions and 94 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2011-01-14 Mike Stump <mikestump@comcast.net>
* config/alpha/alpha.md (umk_mismatch_args): Don't put a mode on set.
* config/fr30/fr30.md: Likweise
(movsi_push): Likewise.
(movsi_pop): Likewise.
(enter_func): Likewise.
* config/moxie/moxie.md (movsi_push): Likewise.
(movsi_pop): Likewise.
2011-01-14 Joseph Myers <joseph@codesourcery.com>
* config/mips/linux64.h (LINK_SPEC): Remove %{bestGnum}

14
gcc/config/alpha/alpha.md
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@ -6910,13 +6910,13 @@
;; Load the CIW into r2 for calling __T3E_MISMATCH
(define_expand "umk_mismatch_args"
[(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
(set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
(set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
(set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
(const_int 8))
(match_dup 2)))
(set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
[(set (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
(set (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
(set (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
(set (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
(const_int 8))
(match_dup 2)))
(set (reg:DI 2) (mem:DI (match_dup 3)))]
"TARGET_ABI_UNICOSMK"
{
operands[1] = gen_reg_rtx (DImode);

2
gcc/config/arm/iwmmxt.md
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@ -551,7 +551,7 @@
;;
;; Note - you cannot use patterns like these here:
;;
;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
;;
;; Because GCC will assume that the truth value (1 or 0) is installed
;; into the entire destination vector, (with the '1' going into the least

164
gcc/config/fr30/fr30.md
View File

@ -140,16 +140,16 @@
;; Push a register onto the stack
(define_insn "movsi_push"
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "register_operand" "a"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "register_operand" "a"))]
""
"st %0, @-r15"
)
;; Pop a register off the stack
(define_insn "movsi_pop"
[(set:SI (match_operand:SI 0 "register_operand" "=a")
(mem:SI (post_inc:SI (reg:SI 15))))]
[(set (match_operand:SI 0 "register_operand" "=a")
(mem:SI (post_inc:SI (reg:SI 15))))]
""
"ld @r15+, %0"
)
@ -292,8 +292,8 @@
"INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128
&& (GET_CODE (operands[0]) != SUBREG
|| SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))"
[(set:SI (match_dup 0) (match_dup 1))
(set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))]
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (sign_extend:SI (match_dup 2)))]
"{
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
operands[2] = gen_lowpart (QImode, operands[0]);
@ -307,8 +307,8 @@
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
[(set:SI (match_dup 0) (match_dup 2))
(parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
[(set (match_dup 0) (match_dup 2))
(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
(clobber (reg:CC 16))])]
"{
HOST_WIDE_INT val = INTVAL (operands[1]);
@ -325,8 +325,8 @@
(match_operand:SI 1 "const_int_operand" ""))]
"(INTVAL (operands[1]) > 0x00ffffff)
&& ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
[(set:SI (match_dup 0) (match_dup 2))
(parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
[(set (match_dup 0) (match_dup 2))
(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
(clobber (reg:CC 16))])]
"{
HOST_WIDE_INT val = INTVAL (operands[1]);
@ -417,108 +417,108 @@
;; is during function prologues and epilogues.
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 3 "high_register_operand" "h"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 3 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 4, 1)"
"stm1 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "high_register_operand" "h"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 3, 1)"
"stm1 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "high_register_operand" "h"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 2, 1)"
"stm1 (%0, %1)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 2 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 3 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
[(set (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 2 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 3 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 4, 0)"
"ldm1 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 2 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
[(set (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 2 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 3, 0)"
"ldm1 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set:SI (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
[(set (match_operand:SI 0 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))
(set (match_operand:SI 1 "high_register_operand" "h")
(mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 2, 0)"
"ldm1 (%0, %1)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 3 "low_register_operand" "l"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 3 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 4, 1)"
"stm0 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "low_register_operand" "l"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 2 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 3, 1)"
"stm0 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
[(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))]
[(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "low_register_operand" "l"))
(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 1 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 2, 1)"
"stm0 (%0, %1)"
[(set_attr "delay_type" "other")]
@ -1210,15 +1210,15 @@
(define_expand "enter_func"
[(parallel
[(set:SI (mem:SI (minus:SI (match_dup 1)
(const_int 4)))
(match_dup 2))
(set:SI (match_dup 2)
(minus:SI (match_dup 1)
(const_int 4)))
(set:SI (match_dup 1)
(minus:SI (match_dup 1)
(match_operand:SI 0 "immediate_operand")))]
[(set (mem:SI (minus:SI (match_dup 1)
(const_int 4)))
(match_dup 2))
(set (match_dup 2)
(minus:SI (match_dup 1)
(const_int 4)))
(set (match_dup 1)
(minus:SI (match_dup 1)
(match_operand:SI 0 "immediate_operand")))]
)]
""
{
@ -1227,15 +1227,15 @@
})
(define_insn "*enter_func"
[(set:SI (mem:SI (minus:SI (reg:SI 15)
(const_int 4)))
(reg:SI 14))
(set:SI (reg:SI 14)
(minus:SI (reg:SI 15)
(const_int 4)))
(set:SI (reg:SI 15)
(minus:SI (reg:SI 15)
(match_operand 0 "immediate_operand" "i")))]
[(set (mem:SI (minus:SI (reg:SI 15)
(const_int 4)))
(reg:SI 14))
(set (reg:SI 14)
(minus:SI (reg:SI 15)
(const_int 4)))
(set (reg:SI 15)
(minus:SI (reg:SI 15)
(match_operand 0 "immediate_operand" "i")))]
"reload_completed"
"enter #%0"
[(set_attr "delay_type" "other")]

8
gcc/config/moxie/moxie.md
View File

@ -188,15 +188,15 @@
;; Push a register onto the stack
(define_insn "movsi_push"
[(set:SI (mem:SI (pre_dec:SI (reg:SI 1)))
(match_operand:SI 0 "register_operand" "r"))]
[(set (mem:SI (pre_dec:SI (reg:SI 1)))
(match_operand:SI 0 "register_operand" "r"))]
""
"push $sp, %0")
;; Pop a register from the stack
(define_insn "movsi_pop"
[(set:SI (match_operand:SI 1 "register_operand" "=r")
(mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))]
[(set (match_operand:SI 1 "register_operand" "=r")
(mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))]
""
"pop %0, %1")