[AArch64] Remove/merge redundant iterators
* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3, bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3, ior<mode>3, xor<mode>3, one_cmpl<mode>2, aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>, aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>, aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed, ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3, reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>, vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>): Change VDQ to VDQ_I. (mul<mode>3): Change VDQM to VDQ_BHSI. (aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>, aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3, aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI. (*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>, aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>, aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>): Change VDW to VD_BHSI. (*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Change VDIC to VD_BHSI. * config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl, saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n, ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI. * config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW, VDIC, VDQQHS): Remove. (Vwtype): Update comment (changing VDW to VD_BHSI). From-SVN: r218310
This commit is contained in:
Alan Lawrence
Alan Lawrence
parent
db97b3b018
commit
a844a69583
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@ -1,3 +1,36 @@
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2014-12-03 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3,
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bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3,
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ior<mode>3, xor<mode>3, one_cmpl<mode>2,
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aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>,
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aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>,
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aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed,
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ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3,
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reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>,
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vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>):
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Change VDQ to VDQ_I.
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(mul<mode>3): Change VDQM to VDQ_BHSI.
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(aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>,
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aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3,
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aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI.
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(*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>,
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aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>,
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aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>):
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Change VDW to VD_BHSI.
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(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>):
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Change VDIC to VD_BHSI.
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* config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl,
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saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n,
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ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI.
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* config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW,
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VDIC, VDQQHS): Remove.
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(Vwtype): Update comment (changing VDW to VD_BHSI).
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2014-12-03 Richard Biener <rguenther@suse.de>
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PR middle-end/14541
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@ -114,20 +114,20 @@
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BUILTIN_VQW (BINOP, ssubw2, 0)
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BUILTIN_VQW (BINOP, usubw2, 0)
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/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */
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BUILTIN_VDW (BINOP, saddl, 0)
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BUILTIN_VDW (BINOP, uaddl, 0)
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BUILTIN_VDW (BINOP, ssubl, 0)
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BUILTIN_VDW (BINOP, usubl, 0)
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BUILTIN_VD_BHSI (BINOP, saddl, 0)
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BUILTIN_VD_BHSI (BINOP, uaddl, 0)
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BUILTIN_VD_BHSI (BINOP, ssubl, 0)
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BUILTIN_VD_BHSI (BINOP, usubl, 0)
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/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */
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BUILTIN_VDW (BINOP, saddw, 0)
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BUILTIN_VDW (BINOP, uaddw, 0)
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BUILTIN_VDW (BINOP, ssubw, 0)
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BUILTIN_VDW (BINOP, usubw, 0)
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BUILTIN_VD_BHSI (BINOP, saddw, 0)
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BUILTIN_VD_BHSI (BINOP, uaddw, 0)
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BUILTIN_VD_BHSI (BINOP, ssubw, 0)
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BUILTIN_VD_BHSI (BINOP, usubw, 0)
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/* Implemented by aarch64_<sur>h<addsub><mode>. */
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BUILTIN_VQ_S (BINOP, shadd, 0)
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BUILTIN_VQ_S (BINOP, uhadd, 0)
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BUILTIN_VQ_S (BINOP, srhadd, 0)
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BUILTIN_VQ_S (BINOP, urhadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
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BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
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/* Implemented by aarch64_<sur><addsub>hn<mode>. */
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BUILTIN_VQN (BINOP, addhn, 0)
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BUILTIN_VQN (BINOP, raddhn, 0)
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@ -202,8 +202,8 @@
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BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
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BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
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/* Implemented by aarch64_<sur>shll_n<mode>. */
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BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
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BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
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BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
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BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
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/* Implemented by aarch64_<sur>shll2_n<mode>. */
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BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
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BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
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@ -42,8 +42,9 @@
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})
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(define_insn "aarch64_simd_dup<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w, w")
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(vec_duplicate:VDQ (match_operand:<VEL> 1 "register_operand" "r, w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w, w")
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(vec_duplicate:VDQ_I
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(match_operand:<VEL> 1 "register_operand" "r, w")))]
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"TARGET_SIMD"
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"@
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dup\\t%0.<Vtype>, %<vw>1
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@ -242,45 +243,45 @@
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])
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(define_insn "orn<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "bic<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(and:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "add<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(plus:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(plus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"add\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "type" "neon_add<q>")]
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)
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(define_insn "sub<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(minus:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(minus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"sub\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "type" "neon_sub<q>")]
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)
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(define_insn "mul<mode>3"
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[(set (match_operand:VDQM 0 "register_operand" "=w")
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(mult:VDQM (match_operand:VDQM 1 "register_operand" "w")
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(match_operand:VDQM 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
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(mult:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")
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(match_operand:VDQ_BHSI 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"mul\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "type" "neon_mul_<Vetype><q>")]
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@ -377,16 +378,16 @@
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)
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(define_insn "neg<mode>2"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(neg:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"neg\t%0.<Vtype>, %1.<Vtype>"
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[(set_attr "type" "neon_neg<q>")]
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)
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(define_insn "abs<mode>2"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(abs:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(abs:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"abs\t%0.<Vtype>, %1.<Vtype>"
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[(set_attr "type" "neon_abs<q>")]
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@ -434,46 +435,46 @@
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)
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(define_insn "and<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "ior<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ior:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "xor<mode>3"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(xor:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(xor:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"eor\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "one_cmpl<mode>2"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(not:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"not\t%0.<Vbtype>, %1.<Vbtype>"
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[(set_attr "type" "neon_logic<q>")]
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)
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(define_insn "aarch64_simd_vec_set<mode>"
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[(set (match_operand:VQ_S 0 "register_operand" "=w,w,w")
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(vec_merge:VQ_S
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(vec_duplicate:VQ_S
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[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w,w,w")
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(vec_merge:VDQ_BHSI
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(vec_duplicate:VDQ_BHSI
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(match_operand:<VEL> 1 "aarch64_simd_general_operand" "r,w,Utv"))
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(match_operand:VQ_S 3 "register_operand" "0,0,0")
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(match_operand:VDQ_BHSI 3 "register_operand" "0,0,0")
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(match_operand:SI 2 "immediate_operand" "i,i,i")))]
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"TARGET_SIMD"
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{
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@ -495,45 +496,45 @@
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)
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(define_insn "aarch64_simd_lshr<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(lshiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(lshiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))]
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"TARGET_SIMD"
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"ushr\t%0.<Vtype>, %1.<Vtype>, %2"
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[(set_attr "type" "neon_shift_imm<q>")]
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)
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(define_insn "aarch64_simd_ashr<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ashiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ashiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))]
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"TARGET_SIMD"
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"sshr\t%0.<Vtype>, %1.<Vtype>, %2"
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[(set_attr "type" "neon_shift_imm<q>")]
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)
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(define_insn "aarch64_simd_imm_shl<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ashift:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "aarch64_simd_lshift_imm" "Dl")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "aarch64_simd_lshift_imm" "Dl")))]
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"TARGET_SIMD"
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"shl\t%0.<Vtype>, %1.<Vtype>, %2"
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[(set_attr "type" "neon_shift_imm<q>")]
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)
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(define_insn "aarch64_simd_reg_sshl<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(ashift:VDQ (match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
[(set_attr "type" "neon_shift_reg<q>")]
|
||||
)
|
||||
|
||||
(define_insn "aarch64_simd_reg_shl<mode>_unsigned"
|
||||
[(set (match_operand:VDQ 0 "register_operand" "=w")
|
||||
(unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")
|
||||
(match_operand:VDQ 2 "register_operand" "w")]
|
||||
[(set (match_operand:VDQ_I 0 "register_operand" "=w")
|
||||
(unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")
|
||||
(match_operand:VDQ_I 2 "register_operand" "w")]
|
||||
UNSPEC_ASHIFT_UNSIGNED))]
|
||||
"TARGET_SIMD"
|
||||
"ushl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
|
|
@ -541,9 +542,9 @@
|
|||
)
|
||||
|
||||
(define_insn "aarch64_simd_reg_shl<mode>_signed"
|
||||
[(set (match_operand:VDQ 0 "register_operand" "=w")
|
||||
(unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")
|
||||
(match_operand:VDQ 2 "register_operand" "w")]
|
||||
[(set (match_operand:VDQ_I 0 "register_operand" "=w")
|
||||
(unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")
|
||||
(match_operand:VDQ_I 2 "register_operand" "w")]
|
||||
UNSPEC_ASHIFT_SIGNED))]
|
||||
"TARGET_SIMD"
|
||||
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
|
|
@ -551,8 +552,8 @@
|
|||
)
|
||||
|
||||
(define_expand "ashl<mode>3"
|
||||
[(match_operand:VDQ 0 "register_operand" "")
|
||||
(match_operand:VDQ 1 "register_operand" "")
|
||||
[(match_operand:VDQ_I 0 "register_operand" "")
|
||||
(match_operand:VDQ_I 1 "register_operand" "")
|
||||
(match_operand:SI 2 "general_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
|
|
@ -598,8 +599,8 @@
|
|||
)
|
||||
|
||||
(define_expand "lshr<mode>3"
|
||||
[(match_operand:VDQ 0 "register_operand" "")
|
||||
(match_operand:VDQ 1 "register_operand" "")
|
||||
[(match_operand:VDQ_I 0 "register_operand" "")
|
||||
(match_operand:VDQ_I 1 "register_operand" "")
|
||||
(match_operand:SI 2 "general_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
|
|
@ -645,8 +646,8 @@
|
|||
)
|
||||
|
||||
(define_expand "ashr<mode>3"
|
||||
[(match_operand:VDQ 0 "register_operand" "")
|
||||
(match_operand:VDQ 1 "register_operand" "")
|
||||
[(match_operand:VDQ_I 0 "register_operand" "")
|
||||
(match_operand:VDQ_I 1 "register_operand" "")
|
||||
(match_operand:SI 2 "general_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
|
|
@ -692,9 +693,9 @@
|
|||
)
|
||||
|
||||
(define_expand "vashl<mode>3"
|
||||
[(match_operand:VDQ 0 "register_operand" "")
|
||||
(match_operand:VDQ 1 "register_operand" "")
|
||||
(match_operand:VDQ 2 "register_operand" "")]
|
||||
[(match_operand:VDQ_I 0 "register_operand" "")
|
||||
(match_operand:VDQ_I 1 "register_operand" "")
|
||||
(match_operand:VDQ_I 2 "register_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
|
||||
|
|
@ -702,13 +703,13 @@
|
|||
DONE;
|
||||
})
|
||||
|
||||
;; Using mode VQ_S as there is no V2DImode neg!
|
||||
;; Using mode VDQ_BHSI as there is no V2DImode neg!
|
||||
;; Negating individual lanes most certainly offsets the
|
||||
;; gain from vectorization.
|
||||
(define_expand "vashr<mode>3"
|
||||
[(match_operand:VQ_S 0 "register_operand" "")
|
||||
(match_operand:VQ_S 1 "register_operand" "")
|
||||
(match_operand:VQ_S 2 "register_operand" "")]
|
||||
[(match_operand:VDQ_BHSI 0 "register_operand" "")
|
||||
(match_operand:VDQ_BHSI 1 "register_operand" "")
|
||||
(match_operand:VDQ_BHSI 2 "register_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx neg = gen_reg_rtx (<MODE>mode);
|
||||
|
|
@ -745,9 +746,9 @@
|
|||
)
|
||||
|
||||
(define_expand "vlshr<mode>3"
|
||||
[(match_operand:VQ_S 0 "register_operand" "")
|
||||
(match_operand:VQ_S 1 "register_operand" "")
|
||||
(match_operand:VQ_S 2 "register_operand" "")]
|
||||
[(match_operand:VDQ_BHSI 0 "register_operand" "")
|
||||
(match_operand:VDQ_BHSI 1 "register_operand" "")
|
||||
(match_operand:VDQ_BHSI 2 "register_operand" "")]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx neg = gen_reg_rtx (<MODE>mode);
|
||||
|
|
@ -783,7 +784,7 @@
|
|||
)
|
||||
|
||||
(define_expand "vec_set<mode>"
|
||||
[(match_operand:VQ_S 0 "register_operand")
|
||||
[(match_operand:VDQ_BHSI 0 "register_operand")
|
||||
(match_operand:<VEL> 1 "register_operand")
|
||||
(match_operand:SI 2 "immediate_operand")]
|
||||
"TARGET_SIMD"
|
||||
|
|
@ -879,10 +880,11 @@
|
|||
|
||||
|
||||
(define_insn "aarch64_mla<mode>"
|
||||
[(set (match_operand:VQ_S 0 "register_operand" "=w")
|
||||
(plus:VQ_S (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w")
|
||||
(match_operand:VQ_S 3 "register_operand" "w"))
|
||||
(match_operand:VQ_S 1 "register_operand" "0")))]
|
||||
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
|
||||
(plus:VDQ_BHSI (mult:VDQ_BHSI
|
||||
(match_operand:VDQ_BHSI 2 "register_operand" "w")
|
||||
(match_operand:VDQ_BHSI 3 "register_operand" "w"))
|
||||
(match_operand:VDQ_BHSI 1 "register_operand" "0")))]
|
||||
"TARGET_SIMD"
|
||||
"mla\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
|
||||
[(set_attr "type" "neon_mla_<Vetype><q>")]
|
||||
|
|
@ -926,10 +928,10 @@
|
|||
)
|
||||
|
||||
(define_insn "aarch64_mls<mode>"
|
||||
[(set (match_operand:VQ_S 0 "register_operand" "=w")
|
||||
(minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0")
|
||||
(mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w")
|
||||
(match_operand:VQ_S 3 "register_operand" "w"))))]
|
||||
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
|
||||
(minus:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "0")
|
||||
(mult:VDQ_BHSI (match_operand:VDQ_BHSI 2 "register_operand" "w")
|
||||
(match_operand:VDQ_BHSI 3 "register_operand" "w"))))]
|
||||
"TARGET_SIMD"
|
||||
"mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
|
||||
[(set_attr "type" "neon_mla_<Vetype><q>")]
|
||||
|
|
@ -974,9 +976,9 @@
|
|||
|
||||
;; Max/Min operations.
|
||||
(define_insn "<su><maxmin><mode>3"
|
||||
[(set (match_operand:VQ_S 0 "register_operand" "=w")
|
||||
(MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w")
|
||||
(match_operand:VQ_S 2 "register_operand" "w")))]
|
||||
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
|
||||
(MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")
|
||||
(match_operand:VDQ_BHSI 2 "register_operand" "w")))]
|
||||
"TARGET_SIMD"
|
||||
"<su><maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
[(set_attr "type" "neon_minmax<q>")]
|
||||
|
|
@ -1314,9 +1316,9 @@
|
|||
(plus:<VWIDE>
|
||||
(mult:<VWIDE>
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 1 "register_operand" "w"))
|
||||
(match_operand:VD_BHSI 1 "register_operand" "w"))
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 2 "register_operand" "w")))
|
||||
(match_operand:VD_BHSI 2 "register_operand" "w")))
|
||||
(match_operand:<VWIDE> 3 "register_operand" "0")))]
|
||||
"TARGET_SIMD"
|
||||
"<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
|
|
@ -1329,9 +1331,9 @@
|
|||
(match_operand:<VWIDE> 1 "register_operand" "0")
|
||||
(mult:<VWIDE>
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 2 "register_operand" "w"))
|
||||
(match_operand:VD_BHSI 2 "register_operand" "w"))
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 3 "register_operand" "w")))))]
|
||||
(match_operand:VD_BHSI 3 "register_operand" "w")))))]
|
||||
"TARGET_SIMD"
|
||||
"<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
|
||||
[(set_attr "type" "neon_mla_<Vetype>_long")]
|
||||
|
|
@ -1826,7 +1828,7 @@
|
|||
|
||||
(define_expand "reduc_plus_scal_<mode>"
|
||||
[(match_operand:<VEL> 0 "register_operand" "=w")
|
||||
(unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")]
|
||||
(unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")]
|
||||
UNSPEC_ADDV)]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
|
|
@ -2033,13 +2035,13 @@
|
|||
})
|
||||
|
||||
(define_expand "aarch64_vcond_internal<mode><mode>"
|
||||
[(set (match_operand:VDQ 0 "register_operand")
|
||||
(if_then_else:VDQ
|
||||
[(set (match_operand:VDQ_I 0 "register_operand")
|
||||
(if_then_else:VDQ_I
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VDQ 4 "register_operand")
|
||||
(match_operand:VDQ 5 "nonmemory_operand")])
|
||||
(match_operand:VDQ 1 "nonmemory_operand")
|
||||
(match_operand:VDQ 2 "nonmemory_operand")))]
|
||||
[(match_operand:VDQ_I 4 "register_operand")
|
||||
(match_operand:VDQ_I 5 "nonmemory_operand")])
|
||||
(match_operand:VDQ_I 1 "nonmemory_operand")
|
||||
(match_operand:VDQ_I 2 "nonmemory_operand")))]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
rtx op1 = operands[1];
|
||||
|
|
@ -2374,13 +2376,13 @@
|
|||
})
|
||||
|
||||
(define_expand "vcondu<mode><mode>"
|
||||
[(set (match_operand:VDQ 0 "register_operand")
|
||||
(if_then_else:VDQ
|
||||
[(set (match_operand:VDQ_I 0 "register_operand")
|
||||
(if_then_else:VDQ_I
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VDQ 4 "register_operand")
|
||||
(match_operand:VDQ 5 "nonmemory_operand")])
|
||||
(match_operand:VDQ 1 "nonmemory_operand")
|
||||
(match_operand:VDQ 2 "nonmemory_operand")))]
|
||||
[(match_operand:VDQ_I 4 "register_operand")
|
||||
(match_operand:VDQ_I 5 "nonmemory_operand")])
|
||||
(match_operand:VDQ_I 1 "nonmemory_operand")
|
||||
(match_operand:VDQ_I 2 "nonmemory_operand")))]
|
||||
"TARGET_SIMD"
|
||||
{
|
||||
emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1],
|
||||
|
|
@ -2476,8 +2478,8 @@
|
|||
(define_insn "*aarch64_combinez<mode>"
|
||||
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
|
||||
(vec_concat:<VDBL>
|
||||
(match_operand:VDIC 1 "register_operand" "w")
|
||||
(match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")))]
|
||||
(match_operand:VD_BHSI 1 "register_operand" "w")
|
||||
(match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")))]
|
||||
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
|
||||
"mov\\t%0.8b, %1.8b"
|
||||
[(set_attr "type" "neon_move<q>")]
|
||||
|
|
@ -2486,8 +2488,8 @@
|
|||
(define_insn "*aarch64_combinez_be<mode>"
|
||||
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
|
||||
(vec_concat:<VDBL>
|
||||
(match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")
|
||||
(match_operand:VDIC 1 "register_operand" "w")))]
|
||||
(match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")
|
||||
(match_operand:VD_BHSI 1 "register_operand" "w")))]
|
||||
"TARGET_SIMD && BYTES_BIG_ENDIAN"
|
||||
"mov\\t%0.8b, %1.8b"
|
||||
[(set_attr "type" "neon_move<q>")]
|
||||
|
|
@ -2626,9 +2628,9 @@
|
|||
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>"
|
||||
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
|
||||
(ADDSUB:<VWIDE> (ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 1 "register_operand" "w"))
|
||||
(match_operand:VD_BHSI 1 "register_operand" "w"))
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 2 "register_operand" "w"))))]
|
||||
(match_operand:VD_BHSI 2 "register_operand" "w"))))]
|
||||
"TARGET_SIMD"
|
||||
"<ANY_EXTEND:su><ADDSUB:optab>l\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
[(set_attr "type" "neon_<ADDSUB:optab>_long")]
|
||||
|
|
@ -2640,7 +2642,7 @@
|
|||
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
|
||||
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
|
||||
(ANY_EXTEND:<VWIDE>
|
||||
(match_operand:VDW 2 "register_operand" "w"))))]
|
||||
(match_operand:VD_BHSI 2 "register_operand" "w"))))]
|
||||
"TARGET_SIMD"
|
||||
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
|
||||
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
|
||||
|
|
@ -2710,9 +2712,9 @@
|
|||
;; <su><r>h<addsub>.
|
||||
|
||||
(define_insn "aarch64_<sur>h<addsub><mode>"
|
||||
[(set (match_operand:VQ_S 0 "register_operand" "=w")
|
||||
(unspec:VQ_S [(match_operand:VQ_S 1 "register_operand" "w")
|
||||
(match_operand:VQ_S 2 "register_operand" "w")]
|
||||
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
|
||||
(unspec:VDQ_BHSI [(match_operand:VDQ_BHSI 1 "register_operand" "w")
|
||||
(match_operand:VDQ_BHSI 2 "register_operand" "w")]
|
||||
HADDSUB))]
|
||||
"TARGET_SIMD"
|
||||
"<sur>h<addsub>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
|
||||
|
|
@ -3519,7 +3521,7 @@
|
|||
|
||||
(define_insn "aarch64_<sur>shll_n<mode>"
|
||||
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
|
||||
(unspec:<VWIDE> [(match_operand:VDW 1 "register_operand" "w")
|
||||
(unspec:<VWIDE> [(match_operand:VD_BHSI 1 "register_operand" "w")
|
||||
(match_operand:SI 2
|
||||
"aarch64_simd_shift_imm_bitsize_<ve_mode>" "i")]
|
||||
VSHLL))]
|
||||
|
|
@ -3633,8 +3635,8 @@
|
|||
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
|
||||
(neg:<V_cmp_result>
|
||||
(COMPARISONS:<V_cmp_result>
|
||||
(match_operand:VDQ 1 "register_operand" "w,w")
|
||||
(match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")
|
||||
(match_operand:VDQ_I 1 "register_operand" "w,w")
|
||||
(match_operand:VDQ_I 2 "aarch64_simd_reg_or_zero" "w,ZDz")
|
||||
)))]
|
||||
"TARGET_SIMD"
|
||||
"@
|
||||
|
|
@ -3698,8 +3700,8 @@
|
|||
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
|
||||
(neg:<V_cmp_result>
|
||||
(UCOMPARISONS:<V_cmp_result>
|
||||
(match_operand:VDQ 1 "register_operand" "w")
|
||||
(match_operand:VDQ 2 "register_operand" "w")
|
||||
(match_operand:VDQ_I 1 "register_operand" "w")
|
||||
(match_operand:VDQ_I 2 "register_operand" "w")
|
||||
)))]
|
||||
"TARGET_SIMD"
|
||||
"cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
|
||||
|
|
@ -3765,10 +3767,10 @@
|
|||
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
|
||||
(plus:<V_cmp_result>
|
||||
(eq:<V_cmp_result>
|
||||
(and:VDQ
|
||||
(match_operand:VDQ 1 "register_operand" "w")
|
||||
(match_operand:VDQ 2 "register_operand" "w"))
|
||||
(match_operand:VDQ 3 "aarch64_simd_imm_zero"))
|
||||
(and:VDQ_I
|
||||
(match_operand:VDQ_I 1 "register_operand" "w")
|
||||
(match_operand:VDQ_I 2 "register_operand" "w"))
|
||||
(match_operand:VDQ_I 3 "aarch64_simd_imm_zero"))
|
||||
(match_operand:<V_cmp_result> 4 "aarch64_simd_imm_minus_one")))
|
||||
]
|
||||
"TARGET_SIMD"
|
||||
|
|
|
|||
|
|
@ -32,18 +32,12 @@
|
|||
;; Iterator for all integer modes (up to 64-bit)
|
||||
(define_mode_iterator ALLI [QI HI SI DI])
|
||||
|
||||
;; Iterator scalar modes (up to 64-bit)
|
||||
(define_mode_iterator SDQ_I [QI HI SI DI])
|
||||
|
||||
;; Iterator for all integer modes that can be extended (up to 64-bit)
|
||||
(define_mode_iterator ALLX [QI HI SI])
|
||||
|
||||
;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
|
||||
(define_mode_iterator GPF [SF DF])
|
||||
|
||||
;; Integer vector modes.
|
||||
(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
|
||||
|
||||
;; Integer vector modes.
|
||||
(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
|
||||
|
||||
|
|
@ -72,16 +66,6 @@
|
|||
;; Quad vector with only 2 element modes.
|
||||
(define_mode_iterator VQ_2E [V2DI V2DF])
|
||||
|
||||
;; All vector modes, except double.
|
||||
(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
|
||||
|
||||
;; Vector and scalar, 64 & 128-bit container: all vector integer mode;
|
||||
;; 8, 16, 32-bit scalar integer modes
|
||||
(define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI])
|
||||
|
||||
;; Vector modes for moves.
|
||||
(define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
|
||||
|
||||
;; This mode iterator allows :P to be used for patterns that operate on
|
||||
;; addresses in different modes. In LP64, only DI will match, while in
|
||||
;; ILP32, either can match.
|
||||
|
|
@ -132,9 +116,6 @@
|
|||
;; All quad integer narrow-able modes.
|
||||
(define_mode_iterator VQN [V8HI V4SI V2DI])
|
||||
|
||||
;; All double integer widen-able modes.
|
||||
(define_mode_iterator VDW [V8QI V4HI V2SI])
|
||||
|
||||
;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
|
||||
(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
|
||||
|
||||
|
|
@ -144,9 +125,6 @@
|
|||
;; Double vector modes for combines.
|
||||
(define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
|
||||
|
||||
;; Double vector modes for combines.
|
||||
(define_mode_iterator VDIC [V8QI V4HI V2SI])
|
||||
|
||||
;; Vector modes except double int.
|
||||
(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
|
||||
|
||||
|
|
@ -159,9 +137,6 @@
|
|||
;; Vector modes for H, S and D types.
|
||||
(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
|
||||
|
||||
;; Vector modes for Q, H and S types.
|
||||
(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI])
|
||||
|
||||
;; Vector and scalar integer modes for H and S
|
||||
(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
|
||||
|
||||
|
|
@ -487,7 +462,7 @@
|
|||
|
||||
)
|
||||
|
||||
;; Widened mode register suffixes for VDW/VQW.
|
||||
;; Widened mode register suffixes for VD_BHSI/VQW.
|
||||
(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
|
||||
(V2SI "2d") (V16QI "8h")
|
||||
(V8HI "4s") (V4SI "2d")])
|
||||
|
|
|
|||
Loading…
Reference in New Issue