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re PR target/59290 ([ARM] regression on negdi-2.c (big-endian))

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[gcc/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* config/arm/arm.md (*zextendsidi_negsi): New pattern.
	* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
	for zero_extend case.

[gcc/testsuite/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* gcc.target/arm/negdi-2.c: Scan more general register names.

From-SVN: r205394
This commit is contained in:
Kyrylo Tkachov 2013-11-26 15:06:06 +00:00 committed by Kyrylo Tkachov
parent 40f213e6f5
commit a866fa46ea
5 changed files with 34 additions and 2 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/59290
* config/arm/arm.md (*zextendsidi_negsi): New pattern.
* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
for zero_extend case.
2013-11-26 H.J. Lu <hongjiu.lu@intel.com>
PR bootstrap/55552

2
gcc/config/arm/arm.c
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@ -10130,6 +10130,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (speed_p)
*cost += 2 * extra_cost->alu.shift;
}
else /* GET_MODE (XEXP (x, 0)) == SImode. */
*cost = COSTS_N_INSNS (1);
/* Widening beyond 32-bits requires one more insn. */
if (mode == DImode)

18
gcc/config/arm/arm.md
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@ -4718,6 +4718,24 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
(define_insn_and_split "*zextendsidi_negsi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
"TARGET_32BIT"
"#"
""
[(set (match_dup 2)
(neg:SI (match_dup 1)))
(set (match_dup 3)
(const_int 0))]
{
operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_highpart (SImode, operands[0]);
}
[(set_attr "length" "8")
(set_attr "type" "multiple")]
)
;; Negate an extended 32-bit value.
(define_insn_and_split "*negdi_extendsidi"
[(set (match_operand:DI 0 "s_register_operand" "=l,r")

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/59290
* gcc.target/arm/negdi-2.c: Scan more general register names.
2013-11-26 Terry Guo <terry.guo@arm.com>
* gcc.target/arm/thumb1-pic-high-reg.c: New case.

4
gcc/testsuite/gcc.target/arm/negdi-2.c
View File

@ -11,6 +11,6 @@ Expected output:
rsb r0, r0, #0
mov r1, #0
*/
/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */
/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */
/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */
/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */
/* { dg-final { scan-assembler-times "mov" 1 } } */