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re PR middle-end/44566 (configuration with multiple targets / backends is not supported.) 

PR other/44566
        * coretypes.h [!USED_FOR_TARGET] (reg_class_t): Define.
        * target.def (struct gcc_target): Replace enum reg_class with
        reg_class_t in hook argument / return types.
        * doc/tm.texi.in (TARGET_SECONDARY_RELOAD): Likewise.
        (TARGET_IRA_COVER_CLASSES, TARGET_MEMORY_MOVE_COST): Likewise.
        (TARGET_BRANCH_TARGET_REGISTER_CLASS): Likewise.
        * targhooks.h (default_branch_target_register_class): Likewise.
        (default_ira_cover_classes, default_secondary_reload): Likewise.
        (default_memory_move_cost, default_register_move_cost): Likewise.
        * targhooks.c (default_branch_target_register_class): Likewise.
        (default_ira_cover_classes, default_secondary_reload): Likewise.
        (default_memory_move_cost, default_register_move_cost): Likewise.
        * reload.c (push_secondary_reload, secondary_reload_class): Likewise.
        * bt-load.c (branch_target_load_optimize): Likewise.
        * ira.c (setup_cover_and_important_classes): Likewise.
        * ira-costs.c (copy_cost): Likewise.
        * reload1.c (emit_input_reload_insns): Likewise.
        * config/alpha/alpha.c (alpha_secondary_reload): Likewise.
        * config/frv/frv.c (frv_secondary_reload): Likewise.
        * config/s390/s390.c (s390_secondary_reload): Likewise.
        * config/i386/i386.c (i386_ira_cover_classes): Likewise.
        (ix86_secondary_reload, ix86_memory_move_cost): Likewise.
        (ix86_register_move_cost): Likewise.
        * config/sh/sh-protos.h (sh_secondary_reload): Likewise.
        * config/sh/sh.c (sh_target_reg_class, sh_secondary_reload): Likewise.
        * config/xtensa/xtensa.c (xtensa_secondary_reload): Likewise.
        * config/xtensa/xtensa-protos.h (xtensa_secondary_reload): Likewise.
        * config/rs6000/rs6000.c (rs6000_secondary_reload): Likewise.
        (rs6000_ira_cover_classes): Likewise.
        * config/picochip/picochip.c (picochip_secondary_reload): Likewise.
        * config/picochip/picochip-protos.h (picochip_secondary_reload):
        Likewise.
        * config/pa/pa.c (pa_secondary_reload): Likewise.
        * config/mips/mips.c (mips_ira_cover_classes): Likewise.
        * config/bfin/bfin.c (bfin_secondary_reload): Likewise.
        * config/ia64/ia64.c (ia64_register_move_cost): Likewise.
        * doc/tm.texi: Regenerate.

From-SVN: r161633
This commit is contained in:
Joern Rennecke 2010-06-30 18:47:43 +00:00 committed by Joern Rennecke
parent 6e44d26e24
commit a87cf97e0d
26 changed files with 175 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
gcc/ChangeLog
View File

@ -1,3 +1,44 @@
2010-06-30 Joern Rennecke <joern.rennecke@embecosm.com>
PR other/44566
* coretypes.h [!USED_FOR_TARGET] (reg_class_t): Define.
* target.def (struct gcc_target): Replace enum reg_class with
reg_class_t in hook argument / return types.
* doc/tm.texi.in (TARGET_SECONDARY_RELOAD): Likewise.
(TARGET_IRA_COVER_CLASSES, TARGET_MEMORY_MOVE_COST): Likewise.
(TARGET_BRANCH_TARGET_REGISTER_CLASS): Likewise.
* targhooks.h (default_branch_target_register_class): Likewise.
(default_ira_cover_classes, default_secondary_reload): Likewise.
(default_memory_move_cost, default_register_move_cost): Likewise.
* targhooks.c (default_branch_target_register_class): Likewise.
(default_ira_cover_classes, default_secondary_reload): Likewise.
(default_memory_move_cost, default_register_move_cost): Likewise.
* reload.c (push_secondary_reload, secondary_reload_class): Likewise.
* bt-load.c (branch_target_load_optimize): Likewise.
* ira.c (setup_cover_and_important_classes): Likewise.
* ira-costs.c (copy_cost): Likewise.
* reload1.c (emit_input_reload_insns): Likewise.
* config/alpha/alpha.c (alpha_secondary_reload): Likewise.
* config/frv/frv.c (frv_secondary_reload): Likewise.
* config/s390/s390.c (s390_secondary_reload): Likewise.
* config/i386/i386.c (i386_ira_cover_classes): Likewise.
(ix86_secondary_reload, ix86_memory_move_cost): Likewise.
(ix86_register_move_cost): Likewise.
* config/sh/sh-protos.h (sh_secondary_reload): Likewise.
* config/sh/sh.c (sh_target_reg_class, sh_secondary_reload): Likewise.
* config/xtensa/xtensa.c (xtensa_secondary_reload): Likewise.
* config/xtensa/xtensa-protos.h (xtensa_secondary_reload): Likewise.
* config/rs6000/rs6000.c (rs6000_secondary_reload): Likewise.
(rs6000_ira_cover_classes): Likewise.
* config/picochip/picochip.c (picochip_secondary_reload): Likewise.
* config/picochip/picochip-protos.h (picochip_secondary_reload):
Likewise.
* config/pa/pa.c (pa_secondary_reload): Likewise.
* config/mips/mips.c (mips_ira_cover_classes): Likewise.
* config/bfin/bfin.c (bfin_secondary_reload): Likewise.
* config/ia64/ia64.c (ia64_register_move_cost): Likewise.
* doc/tm.texi: Regenerate.
2010-06-30 Sebastian Pop <sebastian.pop@amd.com>
PR bootstrrap/44726

3
gcc/bt-load.c
View File

@ -1458,7 +1458,8 @@ migrate_btr_defs (enum reg_class btr_class, int allow_callee_save)
static void
branch_target_load_optimize (bool after_prologue_epilogue_gen)
{
enum reg_class klass = targetm.branch_target_register_class ();
enum reg_class klass
= (enum reg_class) targetm.branch_target_register_class ();
if (klass != NO_REGS)
{
/* Initialize issue_rate. */

6
gcc/config/alpha/alpha.c
View File

@ -1569,10 +1569,12 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
static enum reg_class
alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
static reg_class_t
alpha_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
enum reg_class rclass = (enum reg_class) rclass_i;
/* Loading and storing HImode or QImode values to and from memory
usually requires a scratch register. */
if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))

5
gcc/config/bfin/bfin.c
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@ -2458,8 +2458,8 @@ bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
RCLASS requires an extra scratch register. Return the class needed for the
scratch register. */
static enum reg_class
bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
static reg_class_t
bfin_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
/* If we have HImode or QImode, we can only use DREGS as secondary registers;
@ -2467,6 +2467,7 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS;
enum reg_class x_class = NO_REGS;
enum rtx_code code = GET_CODE (x);
enum reg_class rclass = (enum reg_class) rclass_i;
if (code == SUBREG)
x = SUBREG_REG (x), code = GET_CODE (x);

9
gcc/config/frv/frv.c
View File

@ -1,5 +1,5 @@
/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2008, 2009 Free Software Foundation, Inc.
2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GCC.
@ -384,7 +384,7 @@ static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static void frv_output_dwarf_dtprel (FILE *, int, rtx)
ATTRIBUTE_UNUSED;
static bool frv_secondary_reload (bool, rtx, enum reg_class,
static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
secondary_reload_info *);
static bool frv_frame_pointer_required (void);
@ -6492,12 +6492,13 @@ frv_secondary_reload_class (enum reg_class rclass,
called from init_reg_autoinc() in regclass.c - before the reload optabs
have been initialised. */
static bool
frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
static reg_class_t
frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
enum machine_mode reload_mode,
secondary_reload_info * sri)
{
enum reg_class rclass = NO_REGS;
enum reg_class reload_class = (enum reg_class) reload_class_i;
if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
{

21
gcc/config/i386/i386.c
View File

@ -25287,13 +25287,13 @@ ix86_free_from_memory (enum machine_mode mode)
/* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
same. */
static const enum reg_class *
static const reg_class_t *
i386_ira_cover_classes (void)
{
static const enum reg_class sse_fpmath_classes[] = {
static const reg_class_t sse_fpmath_classes[] = {
GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
};
static const enum reg_class no_sse_fpmath_classes[] = {
static const reg_class_t no_sse_fpmath_classes[] = {
GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
};
@ -25403,8 +25403,8 @@ ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
return regclass;
}
static enum reg_class
ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
static reg_class_t
ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode,
secondary_reload_info *sri ATTRIBUTE_UNUSED)
{
@ -25657,10 +25657,10 @@ inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
}
static int
ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
ix86_memory_move_cost (enum machine_mode mode, reg_class_t regclass,
bool in)
{
return inline_memory_move_cost (mode, regclass, in ? 1 : 0);
return inline_memory_move_cost (mode, (enum reg_class) regclass, in ? 1 : 0);
}
@ -25672,9 +25672,12 @@ ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
general registers. */
static int
ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
enum reg_class class2)
ix86_register_move_cost (enum machine_mode mode, reg_class_t class1_i,
reg_class_t class2_i)
{
enum reg_class class1 = (enum reg_class) class1_i;
enum reg_class class2 = (enum reg_class) class2_i;
/* In case we require secondary memory, compute cost of the store followed
by load. In order to avoid bad register allocation choices, we need
for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */

7
gcc/config/ia64/ia64.c
View File

@ -5207,8 +5207,11 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
one in class TO, using MODE. */
static int
ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
enum reg_class to)
ia64_register_move_cost (enum machine_mode mode, enum reg_class from_i,
enum reg_class to_i)
{
enum reg_class from = (enum reg_class) from_i;
enum reg_class to = (enum reg_class) to_i;
{
/* ADDL_REGS is the same as GR_REGS for movement purposes. */
if (to == ADDL_REGS)

6
gcc/config/mips/mips.c
View File

@ -10929,14 +10929,14 @@ mips_register_move_cost (enum machine_mode mode,
/* Implement TARGET_IRA_COVER_CLASSES. */
static const enum reg_class *
static const reg_class_t *
mips_ira_cover_classes (void)
{
static const enum reg_class acc_classes[] = {
static const reg_class_t acc_classes[] = {
GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
static const enum reg_class no_acc_classes[] = {
static const reg_class_t no_acc_classes[] = {
GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};

11
gcc/config/pa/pa.c
View File

@ -155,9 +155,9 @@ static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static struct machine_function * pa_init_machine_status (void);
static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
enum machine_mode,
secondary_reload_info *);
static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
secondary_reload_info *);
static void pa_extra_live_on_entry (bitmap);
static enum machine_mode pa_promote_function_mode (const_tree,
enum machine_mode, int *,
@ -5688,11 +5688,12 @@ output_arg_descriptor (rtx call_insn)
fputc ('\n', asm_out_file);
}
static enum reg_class
pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
static reg_class_t
pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
int is_symbolic, regno;
enum reg_class rclass = (enum reg_class) rclass_i;
/* Handle the easy stuff first. */
if (rclass == R1_REGS)

4
gcc/config/picochip/picochip-protos.h
View File

@ -73,9 +73,9 @@ extern int picochip_symbol_offset (rtx operand);
extern int picochip_get_function_arg_boundary (enum machine_mode mode);
extern enum reg_class picochip_secondary_reload(bool in_p,
extern reg_class_t picochip_secondary_reload(bool in_p,
rtx x,
enum reg_class cla,
reg_class_t cla,
enum machine_mode mode,
secondary_reload_info *sri);

22
gcc/config/picochip/picochip.c
View File

@ -1,5 +1,5 @@
/* Subroutines used for code generation on picoChip processors.
Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by picoChip Designs Ltd. (http://www.picochip.com)
Maintained by Daniel Towner (daniel.towner@picochip.com) and
Hariharan Sandanagobalane (hariharan@picochip.com)
@ -103,12 +103,12 @@ int picochip_legitimize_reload_address (rtx *x, enum machine_mode mode,
rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
bool outgoing ATTRIBUTE_UNUSED);
enum reg_class
reg_class_t
picochip_secondary_reload (bool in_p,
rtx x ATTRIBUTE_UNUSED,
enum reg_class cla ATTRIBUTE_UNUSED,
enum machine_mode mode,
secondary_reload_info *sri);
rtx x ATTRIBUTE_UNUSED,
reg_class_t cla ATTRIBUTE_UNUSED,
enum machine_mode mode,
secondary_reload_info *sri);
void
picochip_asm_named_section (const char *name,
unsigned int flags ATTRIBUTE_UNUSED,
@ -4363,12 +4363,12 @@ picochip_get_high_const (rtx value)
choice of two registers to choose from, so that we a guaranteed to
get at least one register which is different to the output
register. This trick is taken from the alpha implementation. */
enum reg_class
reg_class_t
picochip_secondary_reload (bool in_p,
rtx x ATTRIBUTE_UNUSED,
enum reg_class cla ATTRIBUTE_UNUSED,
enum machine_mode mode,
secondary_reload_info *sri)
rtx x ATTRIBUTE_UNUSED,
reg_class_t cla ATTRIBUTE_UNUSED,
enum machine_mode mode,
secondary_reload_info *sri)
{
if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
{

21
gcc/config/rs6000/rs6000.c
View File

@ -1240,11 +1240,11 @@ bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
enum reg_class)
= rs6000_cannot_change_mode_class;
static enum reg_class rs6000_secondary_reload (bool, rtx, enum reg_class,
enum machine_mode,
struct secondary_reload_info *);
static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
struct secondary_reload_info *);
static const enum reg_class *rs6000_ira_cover_classes (void);
static const reg_class_t *rs6000_ira_cover_classes (void);
const int INSN_NOT_AVAILABLE = -1;
static enum machine_mode rs6000_eh_return_filter_mode (void);
@ -13728,14 +13728,15 @@ rs6000_reload_register_type (enum reg_class rclass)
For VSX and Altivec, we may need a register to convert sp+offset into
reg+sp. */
static enum reg_class
static reg_class_t
rs6000_secondary_reload (bool in_p,
rtx x,
enum reg_class rclass,
reg_class_t rclass_i,
enum machine_mode mode,
secondary_reload_info *sri)
{
enum reg_class ret = ALL_REGS;
enum reg_class rclass = (enum reg_class) rclass_i;
reg_class_t ret = ALL_REGS;
enum insn_code icode;
bool default_p = false;
@ -14127,11 +14128,11 @@ rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
account for the Altivec and Floating registers being subsets of the VSX
register set under VSX, but distinct register sets on pre-VSX machines. */
static const enum reg_class *
static const reg_class_t *
rs6000_ira_cover_classes (void)
{
static const enum reg_class cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
static const enum reg_class cover_vsx[] = IRA_COVER_CLASSES_VSX;
static const reg_class_t cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
static const reg_class_t cover_vsx[] = IRA_COVER_CLASSES_VSX;
return (TARGET_VSX) ? cover_vsx : cover_pre_vsx;
}

6
gcc/config/s390/s390.c
View File

@ -2957,10 +2957,12 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
static enum reg_class
s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
static reg_class_t
s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
enum reg_class rclass = (enum reg_class) rclass_i;
/* Intermediate register needed. */
if (reg_classes_intersect_p (CC_REGS, rclass))
return GENERAL_REGS;

6
gcc/config/sh/sh-protos.h
View File

@ -173,9 +173,9 @@ extern int sh_contains_memref_p (rtx);
extern int sh_loads_bankedreg_p (rtx);
extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
struct secondary_reload_info;
extern enum reg_class sh_secondary_reload (bool, rtx, enum reg_class,
enum machine_mode,
struct secondary_reload_info *);
extern reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
struct secondary_reload_info *);
extern int sh2a_get_function_vector_number (rtx);
extern int sh2a_is_function_vector_call (rtx);
extern void sh_fix_range (const char *);

10
gcc/config/sh/sh.c
View File

@ -225,7 +225,7 @@ static int sh_variable_issue (FILE *, int, rtx, int);
static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_cannot_modify_jumps_p (void);
static enum reg_class sh_target_reg_class (void);
static reg_class_t sh_target_reg_class (void);
static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree);
@ -10519,7 +10519,7 @@ sh_cannot_modify_jumps_p (void)
return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
}
static enum reg_class
static reg_class_t
sh_target_reg_class (void)
{
return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
@ -12158,10 +12158,12 @@ shmedia_prepare_call_address (rtx fnaddr, int is_sibcall)
return fnaddr;
}
enum reg_class
sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
reg_class_t
sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
enum reg_class rclass = (enum reg_class) rclass_i;
if (in_p)
{
if (REGCLASS_HAS_FP_REG (rclass)

6
gcc/config/xtensa/xtensa-protos.h
View File

@ -67,9 +67,9 @@ extern void xtensa_output_literal (FILE *, rtx, enum machine_mode, int);
extern rtx xtensa_return_addr (int, rtx);
extern enum reg_class xtensa_preferred_reload_class (rtx, enum reg_class, int);
struct secondary_reload_info;
extern enum reg_class xtensa_secondary_reload (bool, rtx, enum reg_class,
enum machine_mode,
struct secondary_reload_info *);
extern reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
struct secondary_reload_info *);
#endif /* RTX_CODE */
#ifdef TREE_CODE

6
gcc/config/xtensa/xtensa.c
View File

@ -1,5 +1,5 @@
/* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
@ -3089,8 +3089,8 @@ xtensa_preferred_reload_class (rtx x, enum reg_class rclass, int isoutput)
}
enum reg_class
xtensa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
reg_class_t
xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode, secondary_reload_info *sri)
{
int regno;

5
gcc/coretypes.h
View File

@ -119,6 +119,11 @@ typedef const struct basic_block_def *const_basic_block;
obstack_chunk_alloc, \
obstack_chunk_free)
/* enum reg_class is target specific, so it should not appear in
target-independent code or interfaces, like the target hook declarations
in target.h. */
typedef int reg_class_t;
#else
struct _dont_use_rtx_here_;

10
gcc/doc/tm.texi
View File

@ -2648,7 +2648,7 @@ Don't define this macro unless the target machine has limitations which
require the macro to do something nontrivial.
@end defmac
@deftypefn {Target Hook} {enum reg_class} TARGET_SECONDARY_RELOAD (bool @var{in_p}, rtx @var{x}, enum reg_class @var{reload_class}, enum machine_mode @var{reload_mode}, secondary_reload_info *@var{sri})
@deftypefn {Target Hook} reg_class_t TARGET_SECONDARY_RELOAD (bool @var{in_p}, rtx @var{x}, reg_class_t @var{reload_class}, enum machine_mode @var{reload_mode}, secondary_reload_info *@var{sri})
Many machines have some registers that cannot be copied directly to or
from memory or even from other types of registers. An example is the
@samp{MQ} register, which on most machines, can only be copied to or
@ -2888,7 +2888,7 @@ as below:
@end smallexample
@end defmac
@deftypefn {Target Hook} {const enum reg_class *} TARGET_IRA_COVER_CLASSES (void)
@deftypefn {Target Hook} {const reg_class_t *} TARGET_IRA_COVER_CLASSES (void)
Return an array of cover classes for the Integrated Register Allocator
(@acronym{IRA}). Cover classes are a set of non-intersecting register
classes covering all hard registers used for register allocation
@ -6122,7 +6122,7 @@ These macros are obsolete, new ports should use the target hook
@code{TARGET_REGISTER_MOVE_COST} instead.
@end defmac
@deftypefn {Target Hook} int TARGET_REGISTER_MOVE_COST (enum machine_mode @var{mode}, enum reg_class @var{from}, enum reg_class @var{to})
@deftypefn {Target Hook} int TARGET_REGISTER_MOVE_COST (enum machine_mode @var{mode}, reg_class_t @var{from}, reg_class_t @var{to})
This target hook should return the cost of moving data of mode @var{mode}
from a register in class @var{from} to one in class @var{to}. The classes
are expressed using the enumeration values such as @code{GENERAL_REGS}.
@ -6170,7 +6170,7 @@ These macros are obsolete, new ports should use the target hook
@code{TARGET_MEMORY_MOVE_COST} instead.
@end defmac
@deftypefn {Target Hook} int TARGET_MEMORY_MOVE_COST (enum machine_mode @var{mode}, enum reg_class @var{rclass}, bool @var{in})
@deftypefn {Target Hook} int TARGET_MEMORY_MOVE_COST (enum machine_mode @var{mode}, reg_class_t @var{rclass}, bool @var{in})
This target hook should return the cost of moving data of mode @var{mode}
between a register of class @var{rclass} and memory; @var{in} is @code{false}
if the value is to be written to memory, @code{true} if it is to be read in.
@ -10944,7 +10944,7 @@ cannot_modify_jumps_past_reload_p ()
@end smallexample
@end deftypefn
@deftypefn {Target Hook} {enum reg_class} TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
@deftypefn {Target Hook} reg_class_t TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
This target hook returns a register class for which branch target register
optimizations should be applied. All registers in this class should be
usable interchangeably. After reload, registers in this class will be

3
gcc/ira-costs.c
View File

@ -156,7 +156,8 @@ copy_cost (rtx x, enum machine_mode mode, enum reg_class rclass, bool to_p,
copy it. */
sri.prev_sri = prev_sri;
sri.extra_cost = 0;
secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);
secondary_class
= (enum reg_class) targetm.secondary_reload (to_p, x, rclass, mode, &sri);
if (secondary_class != NO_REGS)
{

2
gcc/ira.c
View File

@ -740,7 +740,7 @@ setup_cover_and_important_classes (void)
{
int i, j, n, cl;
bool set_p;
const enum reg_class *cover_classes;
const reg_class_t *cover_classes;
HARD_REG_SET temp_hard_regset2;
static enum reg_class classes[LIM_REG_CLASSES + 1];

6
gcc/reload.c
View File

@ -362,7 +362,8 @@ push_secondary_reload (int in_p, rtx x, int opnum, int optional,
sri.icode = CODE_FOR_nothing;
sri.prev_sri = prev_sri;
rclass = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri);
rclass = (enum reg_class) targetm.secondary_reload (in_p, x, reload_class,
reload_mode, &sri);
icode = (enum insn_code) sri.icode;
/* If we don't need any secondary registers, done. */
@ -525,7 +526,8 @@ secondary_reload_class (bool in_p, enum reg_class rclass,
sri.icode = CODE_FOR_nothing;
sri.prev_sri = NULL;
rclass = targetm.secondary_reload (in_p, x, rclass, mode, &sri);
rclass
= (enum reg_class) targetm.secondary_reload (in_p, x, rclass, mode, &sri);
icode = (enum insn_code) sri.icode;
/* If there are no secondary reloads at all, we return NO_REGS.

12
gcc/reload1.c
View File

@ -7506,8 +7506,10 @@ emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
sri.icode = CODE_FOR_nothing;
sri.prev_sri = NULL;
new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
mode, &sri);
new_class
= (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
rl->rclass, mode,
&sri);
if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
second_reload_reg = 0;
@ -7533,8 +7535,10 @@ emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
{
sri2.icode = CODE_FOR_nothing;
sri2.prev_sri = &sri;
new_t_class = targetm.secondary_reload (1, real_oldequiv,
new_class, mode, &sri);
new_t_class
= (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
new_class, mode,
&sri);
if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
{
if (reload_adjust_reg_for_temp (&second_reload_reg,

12
gcc/target.def
View File

@ -1083,7 +1083,7 @@ DEFHOOK
DEFHOOK
(branch_target_register_class,
"",
enum reg_class, (void),
reg_class_t, (void),
default_branch_target_register_class)
/* Return true if branch target register optimizations should include
@ -1362,7 +1362,7 @@ DEFHOOK
DEFHOOK
(register_move_cost,
"",
int, (enum machine_mode mode, enum reg_class from, enum reg_class to),
int, (enum machine_mode mode, reg_class_t from, reg_class_t to),
default_register_move_cost)
/* Compute cost of moving registers to/from memory. */
@ -1371,7 +1371,7 @@ DEFHOOK
DEFHOOK
(memory_move_cost,
"",
int, (enum machine_mode mode, enum reg_class rclass, bool in),
int, (enum machine_mode mode, reg_class_t rclass, bool in),
default_memory_move_cost)
/* True for MODE if the target expects that registers in this mode will
@ -1931,15 +1931,15 @@ DEFHOOK
DEFHOOK
(ira_cover_classes,
"",
const enum reg_class *, (void),
const reg_class_t *, (void),
default_ira_cover_classes)
/* Return the class for a secondary reload, and fill in extra information. */
DEFHOOK
(secondary_reload,
"",
enum reg_class,
(bool in_p, rtx x, enum reg_class reload_class, enum machine_mode reload_mode,
reg_class_t,
(bool in_p, rtx x, reg_class_t reload_class, enum machine_mode reload_mode,
secondary_reload_info *sri),
default_secondary_reload)

23
gcc/targhooks.c
View File

@ -807,28 +807,29 @@ default_return_pops_args (tree fundecl ATTRIBUTE_UNUSED,
return 0;
}
enum reg_class
reg_class_t
default_branch_target_register_class (void)
{
return NO_REGS;
}
#ifdef IRA_COVER_CLASSES
const enum reg_class *
const reg_class_t *
default_ira_cover_classes (void)
{
static enum reg_class classes[] = IRA_COVER_CLASSES;
static reg_class_t classes[] = IRA_COVER_CLASSES;
return classes;
}
#endif
enum reg_class
reg_class_t
default_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED,
enum reg_class reload_class ATTRIBUTE_UNUSED,
reg_class_t reload_class_i ATTRIBUTE_UNUSED,
enum machine_mode reload_mode ATTRIBUTE_UNUSED,
secondary_reload_info *sri)
{
enum reg_class rclass = NO_REGS;
enum reg_class reload_class = (enum reg_class) reload_class_i;
if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
{
@ -1176,13 +1177,13 @@ default_have_conditional_execution (void)
int
default_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
enum reg_class rclass ATTRIBUTE_UNUSED,
reg_class_t rclass ATTRIBUTE_UNUSED,
bool in ATTRIBUTE_UNUSED)
{
#ifndef MEMORY_MOVE_COST
return (4 + memory_move_secondary_cost (mode, rclass, in));
return (4 + memory_move_secondary_cost (mode, (enum reg_class) rclass, in));
#else
return MEMORY_MOVE_COST (mode, rclass, in);
return MEMORY_MOVE_COST (mode, (enum reg_class) rclass, in);
#endif
}
@ -1191,13 +1192,13 @@ default_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
int
default_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
enum reg_class from ATTRIBUTE_UNUSED,
enum reg_class to ATTRIBUTE_UNUSED)
reg_class_t from ATTRIBUTE_UNUSED,
reg_class_t to ATTRIBUTE_UNUSED)
{
#ifndef REGISTER_MOVE_COST
return 2;
#else
return REGISTER_MOVE_COST (mode, from, to);
return REGISTER_MOVE_COST (mode, (enum reg_class) from, (enum reg_class) to);
#endif
}

16
gcc/targhooks.h
View File

@ -115,13 +115,13 @@ extern rtx default_internal_arg_pointer (void);
extern rtx default_static_chain (const_tree, bool);
extern void default_trampoline_init (rtx, tree, rtx);
extern int default_return_pops_args (tree, tree, int);
extern enum reg_class default_branch_target_register_class (void);
extern reg_class_t default_branch_target_register_class (void);
#ifdef IRA_COVER_CLASSES
extern const enum reg_class *default_ira_cover_classes (void);
extern const reg_class_t *default_ira_cover_classes (void);
#endif
extern enum reg_class default_secondary_reload (bool, rtx, enum reg_class,
enum machine_mode,
secondary_reload_info *);
extern reg_class_t default_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
secondary_reload_info *);
extern void default_target_option_override (void);
extern void hook_void_bitmap (bitmap);
extern bool default_handle_c_option (size_t, const char *, int);
@ -147,7 +147,7 @@ extern bool default_addr_space_subset_p (addr_space_t, addr_space_t);
extern rtx default_addr_space_convert (rtx, tree, tree);
extern unsigned int default_case_values_threshold (void);
extern bool default_have_conditional_execution (void);
extern int default_memory_move_cost (enum machine_mode, enum reg_class, bool);
extern int default_register_move_cost (enum machine_mode, enum reg_class,
enum reg_class);
extern int default_memory_move_cost (enum machine_mode, reg_class_t, bool);
extern int default_register_move_cost (enum machine_mode, reg_class_t,
reg_class_t);