i386: Emulate MMX mmx_uavgv8qi3 with SSE
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. From-SVN: r271235
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2019-05-15 H.J. Lu <hongjiu.lu@intel.com>
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PR target/89021
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* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
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and TARGET_MMX_WITH_SSE.
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(*mmx_uavgv8qi3): Add SSE emulation.
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2019-05-15 H.J. Lu <hongjiu.lu@intel.com>
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PR target/89021
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@ -1704,50 +1704,55 @@
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(plus:V8HI
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(plus:V8HI
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(zero_extend:V8HI
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(match_operand:V8QI 1 "nonimmediate_operand"))
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(match_operand:V8QI 1 "register_mmxmem_operand"))
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(zero_extend:V8HI
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(match_operand:V8QI 2 "nonimmediate_operand")))
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(match_operand:V8QI 2 "register_mmxmem_operand")))
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(const_vector:V8HI [(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)]))
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(const_int 1))))]
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"TARGET_SSE || TARGET_3DNOW"
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"(TARGET_MMX || TARGET_MMX_WITH_SSE)
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&& (TARGET_SSE || TARGET_3DNOW_A)"
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"ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
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(define_insn "*mmx_uavgv8qi3"
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[(set (match_operand:V8QI 0 "register_operand" "=y")
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[(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
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(truncate:V8QI
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(lshiftrt:V8HI
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(plus:V8HI
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(plus:V8HI
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(zero_extend:V8HI
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(match_operand:V8QI 1 "nonimmediate_operand" "%0"))
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(match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yv"))
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(zero_extend:V8HI
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(match_operand:V8QI 2 "nonimmediate_operand" "ym")))
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(match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")))
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(const_vector:V8HI [(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)
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(const_int 1) (const_int 1)]))
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(const_int 1))))]
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"(TARGET_SSE || TARGET_3DNOW)
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"(TARGET_MMX || TARGET_MMX_WITH_SSE)
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&& (TARGET_SSE || TARGET_3DNOW_A)
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&& ix86_binary_operator_ok (PLUS, V8QImode, operands)"
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{
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/* These two instructions have the same operation, but their encoding
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is different. Prefer the one that is de facto standard. */
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if (TARGET_SSE || TARGET_3DNOW_A)
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if (TARGET_MMX_WITH_SSE && TARGET_AVX)
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return "vpavgb\t{%2, %1, %0|%0, %1, %2}";
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else if (TARGET_SSE || TARGET_3DNOW_A)
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return "pavgb\t{%2, %0|%0, %2}";
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else
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return "pavgusb\t{%2, %0|%0, %2}";
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}
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[(set_attr "type" "mmxshft")
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[(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
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(set_attr "type" "mmxshft,sseiadd,sseiadd")
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(set (attr "prefix_extra")
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(if_then_else
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(not (ior (match_test "TARGET_SSE")
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(match_test "TARGET_3DNOW_A")))
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(const_string "1")
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(const_string "*")))
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(set_attr "mode" "DI")])
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(set_attr "mode" "DI,TI,TI")])
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(define_expand "mmx_uavgv4hi3"
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[(set (match_operand:V4HI 0 "register_operand")
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