Revert "[ARM] Fix PR85434: spilling of stack protector guard's address on ARM"
This reverts commit r263245. From-SVN: r263252
This commit is contained in:
Thomas Preud'homme
parent
0016d8d91c
commit
a8b2130aee
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@ -89,44 +89,6 @@
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(process_file): Move functions processing to
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process_all_functions.
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2018-08-02 Thomas Preud'homme <thomas.preudhomme@linaro.org>
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PR target/85434
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* target-insns.def (stack_protect_combined_set): Define new standard
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pattern name.
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(stack_protect_combined_test): Likewise.
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* cfgexpand.c (stack_protect_prologue): Try new
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stack_protect_combined_set pattern first.
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* function.c (stack_protect_epilogue): Try new
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stack_protect_combined_test pattern first.
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* config/arm/arm.c (require_pic_register): Add pic_reg and compute_now
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parameters to control which register to use as PIC register and force
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reloading PIC register respectively. Insert in the stream of insns if
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possible.
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(legitimize_pic_address): Expose above new parameters in prototype and
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adapt recursive calls accordingly.
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(arm_legitimize_address): Adapt to new legitimize_pic_address
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prototype.
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(thumb_legitimize_address): Likewise.
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(arm_emit_call_insn): Adapt to new require_pic_register prototype.
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* config/arm/arm-protos.h (legitimize_pic_address): Adapt to prototype
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change.
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* config/arm/arm.md (movsi expander): Adapt to legitimize_pic_address
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prototype change.
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(stack_protect_combined_set): New insn_and_split pattern.
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(stack_protect_set): New insn pattern.
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(stack_protect_combined_test): New insn_and_split pattern.
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(stack_protect_test): New insn pattern.
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* config/arm/unspecs.md (UNSPEC_SP_SET): New unspec.
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(UNSPEC_SP_TEST): Likewise.
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* doc/md.texi (stack_protect_combined_set): Document new standard
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pattern name.
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(stack_protect_set): Clarify that the operand for guard's address is
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legal.
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(stack_protect_combined_test): Document new standard pattern name.
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(stack_protect_test): Clarify that the operand for guard's address is
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legal.
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2018-08-02 David Malcolm <dmalcolm@redhat.com>
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* dumpfile.c (dump_user_location_t::dump_user_location_t): Add
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@ -6105,18 +6105,8 @@ stack_protect_prologue (void)
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{
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tree guard_decl = targetm.stack_protect_guard ();
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rtx x, y;
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struct expand_operand ops[2];
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x = expand_normal (crtl->stack_protect_guard);
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create_fixed_operand (&ops[0], x);
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create_fixed_operand (&ops[1], DECL_RTL (guard_decl));
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/* Allow the target to compute address of Y and copy it to X without
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leaking Y into a register. This combined address + copy pattern allows
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the target to prevent spilling of any intermediate results by splitting
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it after register allocator. */
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if (maybe_expand_insn (targetm.code_for_stack_protect_combined_set, 2, ops))
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return;
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if (guard_decl)
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y = expand_normal (guard_decl);
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else
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@ -67,7 +67,7 @@ extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
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extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
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HOST_WIDE_INT, rtx, rtx, int);
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extern int legitimate_pic_operand_p (rtx);
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extern rtx legitimize_pic_address (rtx, machine_mode, rtx, rtx, bool);
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extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
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extern rtx legitimize_tls_address (rtx, rtx);
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extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
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extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
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@ -7369,26 +7369,20 @@ legitimate_pic_operand_p (rtx x)
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}
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/* Record that the current function needs a PIC register. Initialize
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cfun->machine->pic_reg if we have not already done so.
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A new pseudo register is used for the PIC register if possible, otherwise
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PIC_REG must be non NULL and is used instead. COMPUTE_NOW forces the PIC
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register to be loaded, irregardless of whether it was loaded previously. */
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cfun->machine->pic_reg if we have not already done so. */
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static void
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require_pic_register (rtx pic_reg, bool compute_now)
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require_pic_register (void)
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{
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/* A lot of the logic here is made obscure by the fact that this
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routine gets called as part of the rtx cost estimation process.
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We don't want those calls to affect any assumptions about the real
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function; and further, we can't call entry_of_function() until we
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start the real expansion process. */
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if (!crtl->uses_pic_offset_table || compute_now)
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if (!crtl->uses_pic_offset_table)
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{
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gcc_assert (can_create_pseudo_p ()
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|| (pic_reg != NULL_RTX && GET_MODE (pic_reg) == Pmode));
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gcc_assert (can_create_pseudo_p ());
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if (arm_pic_register != INVALID_REGNUM
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&& can_create_pseudo_p ()
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&& !(TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM))
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{
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if (!cfun->machine->pic_reg)
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@ -7405,8 +7399,7 @@ require_pic_register (rtx pic_reg, bool compute_now)
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rtx_insn *seq, *insn;
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if (!cfun->machine->pic_reg)
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cfun->machine->pic_reg =
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can_create_pseudo_p () ? gen_reg_rtx (Pmode) : pic_reg;
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cfun->machine->pic_reg = gen_reg_rtx (Pmode);
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/* Play games to avoid marking the function as needing pic
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if we are being called as part of the cost-estimation
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@ -7417,8 +7410,7 @@ require_pic_register (rtx pic_reg, bool compute_now)
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start_sequence ();
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if (TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM
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&& arm_pic_register > LAST_LO_REGNUM
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&& can_create_pseudo_p ())
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&& arm_pic_register > LAST_LO_REGNUM)
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emit_move_insn (cfun->machine->pic_reg,
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gen_rtx_REG (Pmode, arm_pic_register));
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else
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@ -7435,29 +7427,15 @@ require_pic_register (rtx pic_reg, bool compute_now)
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we can't yet emit instructions directly in the final
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insn stream. Queue the insns on the entry edge, they will
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be committed after everything else is expanded. */
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if (currently_expanding_to_rtl)
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insert_insn_on_edge (seq,
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single_succ_edge
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(ENTRY_BLOCK_PTR_FOR_FN (cfun)));
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else
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emit_insn (seq);
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insert_insn_on_edge (seq,
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single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun)));
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}
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}
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}
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}
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/* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is
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created to hold the result of the load. If not NULL, PIC_REG indicates
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which register to use as PIC register, otherwise it is decided by register
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allocator. COMPUTE_NOW forces the PIC register to be loaded at the current
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location in the instruction stream, irregardless of whether it was loaded
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previously.
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Returns the register REG into which the PIC load is performed. */
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rtx
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legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
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bool compute_now)
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legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
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{
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if (GET_CODE (orig) == SYMBOL_REF
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|| GET_CODE (orig) == LABEL_REF)
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@ -7491,7 +7469,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
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rtx mem;
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/* If this function doesn't have a pic register, create one now. */
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require_pic_register (pic_reg, compute_now);
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require_pic_register ();
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pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig);
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@ -7542,11 +7520,9 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
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gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
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base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg,
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pic_reg, compute_now);
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base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
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offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
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base == reg ? 0 : reg, pic_reg,
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compute_now);
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base == reg ? 0 : reg);
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if (CONST_INT_P (offset))
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{
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@ -8731,8 +8707,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
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{
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/* We need to find and carefully transform any SYMBOL and LABEL
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references; so go back to the original address expression. */
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rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX, NULL_RTX,
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false /*compute_now*/);
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rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
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if (new_x != orig_x)
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x = new_x;
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@ -8800,8 +8775,7 @@ thumb_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
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{
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/* We need to find and carefully transform any SYMBOL and LABEL
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references; so go back to the original address expression. */
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rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX, NULL_RTX,
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false /*compute_now*/);
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rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
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if (new_x != orig_x)
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x = new_x;
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@ -18085,7 +18059,7 @@ arm_emit_call_insn (rtx pat, rtx addr, bool sibcall)
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? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
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: !SYMBOL_REF_LOCAL_P (addr)))
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{
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require_pic_register (NULL_RTX, false /*compute_now*/);
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require_pic_register ();
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use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
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}
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@ -6021,8 +6021,7 @@
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operands[1] = legitimize_pic_address (operands[1], SImode,
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(!can_create_pseudo_p ()
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? operands[0]
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: NULL_RTX), NULL_RTX,
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false /*compute_now*/);
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: 0));
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}
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"
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)
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@ -8635,95 +8634,6 @@
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(set_attr "conds" "clob")]
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)
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;; Named patterns for stack smashing protection.
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(define_insn_and_split "stack_protect_combined_set"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(unspec:SI [(match_operand:SI 1 "memory_operand" "X")]
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UNSPEC_SP_SET))
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(match_scratch:SI 2 "=r")
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(match_scratch:SI 3 "=r")]
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""
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"#"
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"reload_completed"
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[(parallel [(set (match_dup 0) (unspec:SI [(mem:SI (match_dup 2))]
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UNSPEC_SP_SET))
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(clobber (match_dup 2))])]
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"
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{
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rtx addr = XEXP (operands[1], 0);
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if (flag_pic)
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{
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/* Forces recomputing of GOT base now. */
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operands[1] = legitimize_pic_address (addr, SImode, operands[2],
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operands[3], true /*compute_now*/);
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}
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else
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{
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if (!address_operand (addr, SImode))
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operands[1] = force_const_mem (SImode, addr);
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emit_move_insn (operands[2], operands[1]);
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}
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}"
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)
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(define_insn "stack_protect_set"
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[(set (match_operand:SI 0 "memory_operand" "=m")
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(unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "r"))]
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UNSPEC_SP_SET))
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(clobber (match_dup 1))]
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""
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"ldr\\t%1, [%1]\;str\\t%1, %0\;mov\t%1,0"
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[(set_attr "length" "12")
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(set_attr "type" "multiple")])
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(define_insn_and_split "stack_protect_combined_test"
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[(set (pc)
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(if_then_else
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(eq (match_operand:SI 0 "memory_operand" "m")
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(unspec:SI [(match_operand:SI 1 "memory_operand" "X")]
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UNSPEC_SP_TEST))
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(label_ref (match_operand 2))
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(pc)))
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(match_scratch:SI 3 "=r")
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(match_scratch:SI 4 "=r")]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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rtx eq, addr;
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addr = XEXP (operands[1], 0);
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if (flag_pic)
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{
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/* Forces recomputing of GOT base now. */
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operands[1] = legitimize_pic_address (addr, SImode, operands[3],
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operands[4],
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true /*compute_now*/);
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}
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else
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{
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if (!address_operand (addr, SImode))
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operands[1] = force_const_mem (SImode, addr);
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emit_move_insn (operands[3], operands[1]);
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}
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emit_insn (gen_stack_protect_test (operands[4], operands[0], operands[3]));
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eq = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
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emit_jump_insn (gen_cbranchsi4 (eq, operands[4], const0_rtx, operands[2]));
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DONE;
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})
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(define_insn "stack_protect_test"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
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(mem:SI (match_operand:SI 2 "register_operand" "r"))]
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UNSPEC_SP_TEST))
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(clobber (match_dup 2))]
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""
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"ldr\t%0, [%2]\;ldr\t%2, %1\;eor\t%0, %2, %0"
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[(set_attr "length" "12")
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(set_attr "type" "multiple")])
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(define_expand "casesi"
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[(match_operand:SI 0 "s_register_operand" "") ; index to jump on
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(match_operand:SI 1 "const_int_operand" "") ; lower bound
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@ -86,9 +86,6 @@
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UNSPEC_PROBE_STACK ; Probe stack memory reference
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UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with
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; security extension
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UNSPEC_SP_SET ; Represent the setting of stack protector's canary
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UNSPEC_SP_TEST ; Represent the testing of stack protector's canary
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; against the guard.
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])
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(define_c_enum "unspec" [
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@ -7388,61 +7388,22 @@ builtins.
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The get/set patterns have a single output/input operand respectively,
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with @var{mode} intended to be @code{Pmode}.
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@cindex @code{stack_protect_combined_set} instruction pattern
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@item @samp{stack_protect_combined_set}
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This pattern, if defined, moves a @code{ptr_mode} value from an address
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whose declaration RTX is given in operand 1 to the memory in operand 0
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without leaving the value in a register afterward. If several
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instructions are needed by the target to perform the operation (eg. to
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load the address from a GOT entry then load the @code{ptr_mode} value
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and finally store it), it is the backend's responsibility to ensure no
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intermediate result gets spilled. This is to avoid leaking the value
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some place that an attacker might use to rewrite the stack guard slot
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after having clobbered it.
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If this pattern is not defined, then the address declaration is
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expanded first in the standard way and a @code{stack_protect_set}
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pattern is then generated to move the value from that address to the
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address in operand 0.
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@cindex @code{stack_protect_set} instruction pattern
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@item @samp{stack_protect_set}
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This pattern, if defined, moves a @code{ptr_mode} value from the valid
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memory location in operand 1 to the memory in operand 0 without leaving
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the value in a register afterward. This is to avoid leaking the value
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some place that an attacker might use to rewrite the stack guard slot
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after having clobbered it.
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Note: on targets where the addressing modes do not allow to load
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directly from stack guard address, the address is expanded in a standard
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way first which could cause some spills.
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This pattern, if defined, moves a @code{ptr_mode} value from the memory
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in operand 1 to the memory in operand 0 without leaving the value in
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a register afterward. This is to avoid leaking the value some place
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that an attacker might use to rewrite the stack guard slot after
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having clobbered it.
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If this pattern is not defined, then a plain move pattern is generated.
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@cindex @code{stack_protect_combined_test} instruction pattern
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@item @samp{stack_protect_combined_test}
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This pattern, if defined, compares a @code{ptr_mode} value from an
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address whose declaration RTX is given in operand 1 with the memory in
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operand 0 without leaving the value in a register afterward and
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branches to operand 2 if the values were equal. If several
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instructions are needed by the target to perform the operation (eg. to
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load the address from a GOT entry then load the @code{ptr_mode} value
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and finally store it), it is the backend's responsibility to ensure no
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intermediate result gets spilled. This is to avoid leaking the value
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some place that an attacker might use to rewrite the stack guard slot
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after having clobbered it.
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If this pattern is not defined, then the address declaration is
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expanded first in the standard way and a @code{stack_protect_test}
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pattern is then generated to compare the value from that address to the
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value at the memory in operand 0.
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@cindex @code{stack_protect_test} instruction pattern
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@item @samp{stack_protect_test}
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This pattern, if defined, compares a @code{ptr_mode} value from the
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valid memory location in operand 1 with the memory in operand 0 without
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leaving the value in a register afterward and branches to operand 2 if
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the values were equal.
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memory in operand 1 with the memory in operand 0 without leaving the
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value in a register afterward and branches to operand 2 if the values
|
||||
were equal.
|
||||
|
||||
If this pattern is not defined, then a plain compare pattern and
|
||||
conditional branch pattern is used.
|
||||
|
|
|
|||
|
|
@ -4893,33 +4893,20 @@ stack_protect_epilogue (void)
|
|||
rtx_code_label *label = gen_label_rtx ();
|
||||
rtx x, y;
|
||||
rtx_insn *seq;
|
||||
struct expand_operand ops[3];
|
||||
|
||||
x = expand_normal (crtl->stack_protect_guard);
|
||||
create_fixed_operand (&ops[0], x);
|
||||
create_fixed_operand (&ops[1], DECL_RTL (guard_decl));
|
||||
create_fixed_operand (&ops[2], label);
|
||||
/* Allow the target to compute address of Y and compare it with X without
|
||||
leaking Y into a register. This combined address + compare pattern allows
|
||||
the target to prevent spilling of any intermediate results by splitting
|
||||
it after register allocator. */
|
||||
if (!maybe_expand_jump_insn (targetm.code_for_stack_protect_combined_test,
|
||||
3, ops))
|
||||
{
|
||||
if (guard_decl)
|
||||
y = expand_normal (guard_decl);
|
||||
else
|
||||
y = const0_rtx;
|
||||
if (guard_decl)
|
||||
y = expand_normal (guard_decl);
|
||||
else
|
||||
y = const0_rtx;
|
||||
|
||||
/* Allow the target to compare Y with X without leaking either into
|
||||
a register. */
|
||||
if (targetm.have_stack_protect_test ()
|
||||
&& ((seq = targetm.gen_stack_protect_test (x, y, label))
|
||||
!= NULL_RTX))
|
||||
emit_insn (seq);
|
||||
else
|
||||
emit_cmp_and_jump_insns (x, y, EQ, NULL_RTX, ptr_mode, 1, label);
|
||||
}
|
||||
/* Allow the target to compare Y with X without leaking either into
|
||||
a register. */
|
||||
if (targetm.have_stack_protect_test ()
|
||||
&& ((seq = targetm.gen_stack_protect_test (x, y, label)) != NULL_RTX))
|
||||
emit_insn (seq);
|
||||
else
|
||||
emit_cmp_and_jump_insns (x, y, EQ, NULL_RTX, ptr_mode, 1, label);
|
||||
|
||||
/* The noreturn predictor has been moved to the tree level. The rtl-level
|
||||
predictors estimate this branch about 20%, which isn't enough to get
|
||||
|
|
|
|||
|
|
@ -96,9 +96,7 @@ DEF_TARGET_INSN (sibcall_value, (rtx x0, rtx x1, rtx opt2, rtx opt3,
|
|||
DEF_TARGET_INSN (simple_return, (void))
|
||||
DEF_TARGET_INSN (split_stack_prologue, (void))
|
||||
DEF_TARGET_INSN (split_stack_space_check, (rtx x0, rtx x1))
|
||||
DEF_TARGET_INSN (stack_protect_combined_set, (rtx x0, rtx x1))
|
||||
DEF_TARGET_INSN (stack_protect_set, (rtx x0, rtx x1))
|
||||
DEF_TARGET_INSN (stack_protect_combined_test, (rtx x0, rtx x1, rtx x2))
|
||||
DEF_TARGET_INSN (stack_protect_test, (rtx x0, rtx x1, rtx x2))
|
||||
DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2))
|
||||
DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1))
|
||||
|
|
|
|||
|
|
@ -15,11 +15,6 @@
|
|||
PR target/86014
|
||||
* gcc.target/aarch64/ldp_stp_13.c: New test.
|
||||
|
||||
2018-08-02 Thomas Preud'homme <thomas.preudhomme@linaro.org>
|
||||
|
||||
PR target/85434
|
||||
* gcc.target/arm/pr85434.c: New test.
|
||||
|
||||
2018-08-01 Martin Sebor <msebor@redhat.com>
|
||||
|
||||
PR tree-optimization/86650
|
||||
|
|
|
|||
|
|
@ -1,200 +0,0 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target fstack_protector }*/
|
||||
/* { dg-require-effective-target fpic }*/
|
||||
/* { dg-additional-options "-Os -fpic -fstack-protector-strong" } */
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
static const unsigned char base64_enc_map[64] =
|
||||
{
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J',
|
||||
'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
|
||||
'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd',
|
||||
'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
|
||||
'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x',
|
||||
'y', 'z', '0', '1', '2', '3', '4', '5', '6', '7',
|
||||
'8', '9', '+', '/'
|
||||
};
|
||||
|
||||
#define BASE64_SIZE_T_MAX ( (size_t) -1 ) /* SIZE_T_MAX is not standard */
|
||||
|
||||
|
||||
void doSmth(void *x);
|
||||
|
||||
#include <string.h>
|
||||
|
||||
|
||||
void check(int n) {
|
||||
|
||||
if (!(n % 2 && n % 3 && n % 5)) {
|
||||
__asm__ ( "add r8, r8, #1;" );
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t test(
|
||||
uint32_t a1,
|
||||
uint32_t a2,
|
||||
size_t a3,
|
||||
size_t a4,
|
||||
size_t a5,
|
||||
size_t a6)
|
||||
{
|
||||
uint32_t nResult = 0;
|
||||
uint8_t* h = 0L;
|
||||
uint8_t X[128];
|
||||
uint8_t mac[64];
|
||||
size_t len;
|
||||
|
||||
doSmth(&a1);
|
||||
doSmth(&a2);
|
||||
doSmth(&a3);
|
||||
doSmth(&a4);
|
||||
doSmth(&a5);
|
||||
doSmth(&a6);
|
||||
|
||||
if (a1 && a2 && a3 && a4 && a5 && a6) {
|
||||
nResult = 1;
|
||||
h = (void*)X;
|
||||
len = sizeof(X);
|
||||
memset(X, a2, len);
|
||||
len -= 64;
|
||||
memcpy(mac ,X, len);
|
||||
*(h + len) = a6;
|
||||
|
||||
{
|
||||
|
||||
|
||||
unsigned char *dst = X;
|
||||
size_t dlen = a3;
|
||||
size_t *olen = &a6;
|
||||
const unsigned char *src = mac;
|
||||
size_t slen = a4;
|
||||
size_t i, n;
|
||||
int C1, C2, C3;
|
||||
unsigned char *p;
|
||||
|
||||
if( slen == 0 )
|
||||
{
|
||||
*olen = 0;
|
||||
return( 0 );
|
||||
}
|
||||
|
||||
n = slen / 3 + ( slen % 3 != 0 );
|
||||
|
||||
if( n > ( BASE64_SIZE_T_MAX - 1 ) / 4 )
|
||||
{
|
||||
*olen = BASE64_SIZE_T_MAX;
|
||||
return( 0 );
|
||||
}
|
||||
|
||||
n *= 4;
|
||||
|
||||
if( ( dlen < n + 1 ) || ( NULL == dst ) )
|
||||
{
|
||||
*olen = n + 1;
|
||||
return( 0 );
|
||||
}
|
||||
|
||||
n = ( slen / 3 ) * 3;
|
||||
|
||||
for( i = 0, p = dst; i < n; i += 3 )
|
||||
{
|
||||
C1 = *src++;
|
||||
C2 = *src++;
|
||||
C3 = *src++;
|
||||
|
||||
check(i);
|
||||
|
||||
*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
|
||||
*p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F];
|
||||
*p++ = base64_enc_map[(((C2 & 15) << 2) + (C3 >> 6)) & 0x3F];
|
||||
*p++ = base64_enc_map[C3 & 0x3F];
|
||||
}
|
||||
|
||||
if( i < slen )
|
||||
{
|
||||
C1 = *src++;
|
||||
C2 = ( ( i + 1 ) < slen ) ? *src++ : 0;
|
||||
|
||||
*p++ = base64_enc_map[(C1 >> 2) & 0x3F];
|
||||
*p++ = base64_enc_map[(((C1 & 3) << 4) + (C2 >> 4)) & 0x3F];
|
||||
|
||||
if( ( i + 1 ) < slen )
|
||||
*p++ = base64_enc_map[((C2 & 15) << 2) & 0x3F];
|
||||
else *p++ = '=';
|
||||
|
||||
*p++ = '=';
|
||||
}
|
||||
|
||||
*olen = p - dst;
|
||||
*p = 0;
|
||||
|
||||
}
|
||||
|
||||
__asm__ ("mov r8, %0;" : "=r" ( nResult ));
|
||||
}
|
||||
else
|
||||
{
|
||||
nResult = 2;
|
||||
}
|
||||
|
||||
doSmth(X);
|
||||
doSmth(mac);
|
||||
|
||||
|
||||
return nResult;
|
||||
}
|
||||
|
||||
/* The pattern below catches sequences of instructions that were generated
|
||||
for ARM and Thumb-2 before the fix for this PR. They are of the form:
|
||||
|
||||
ldr rX, <offset from sp or fp>
|
||||
<optional non ldr instructions>
|
||||
ldr rY, <offset from sp or fp>
|
||||
ldr rZ, [rX]
|
||||
<optional non ldr instructions>
|
||||
cmp rY, rZ
|
||||
<optional non cmp instructions>
|
||||
bl __stack_chk_fail
|
||||
|
||||
Ideally the optional block would check for the various rX, rY and rZ
|
||||
registers not being set but this is not possible due to back references
|
||||
being illegal in lookahead expression in Tcl, thus preventing to use the
|
||||
only construct that allow to negate a regexp from using the backreferences
|
||||
to those registers. Instead we go for the heuristic of allowing non ldr/cmp
|
||||
instructions with the assumptions that (i) those are not part of the stack
|
||||
protector sequences and (ii) they would only be scheduled here if they don't
|
||||
conflict with registers used by stack protector.
|
||||
|
||||
Note on the regexp logic:
|
||||
Allowing non X instructions (where X is ldr or cmp) is done by looking for
|
||||
some non newline spaces, followed by something which is not X, followed by
|
||||
an alphanumeric character followed by anything but a newline and ended by a
|
||||
newline the whole thing an undetermined number of times. The alphanumeric
|
||||
character is there to force the match of the negative lookahead for X to
|
||||
only happen after all the initial spaces and thus to check the mnemonic.
|
||||
This prevents it to match one of the initial space. */
|
||||
/* { dg-final { scan-assembler-not {ldr[ \t]+([^,]+), \[(?:sp|fp)[^]]*\](?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+ldr[ \t]+([^,]+), \[(?:sp|fp)[^]]*\]\n[ \t]+ldr[ \t]+([^,]+), \[\1\](?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+cmp[ \t]+\2, \3(?:\n[ \t]+(?!cmp)\w[^\n]*)*\n[ \t]+bl[ \t]+__stack_chk_fail} } } */
|
||||
|
||||
/* Likewise for Thumb-1 sequences of instructions prior to the fix for this PR
|
||||
which had the form:
|
||||
|
||||
ldr rS, <offset from sp or fp>
|
||||
<optional non ldr instructions>
|
||||
ldr rT, <PC relative offset>
|
||||
<optional non ldr instructions>
|
||||
ldr rX, [rS, rT]
|
||||
<optional non ldr instructions>
|
||||
ldr rY, <offset from sp or fp>
|
||||
ldr rZ, [rX]
|
||||
<optional non ldr instructions>
|
||||
cmp rY, rZ
|
||||
<optional non cmp instructions>
|
||||
bl __stack_chk_fail
|
||||
|
||||
Note on the regexp logic:
|
||||
PC relative offset is checked by looking for a source operand that does not
|
||||
contain [ or ]. */
|
||||
/* { dg-final { scan-assembler-not {ldr[ \t]+([^,]+), \[(?:sp|fp)[^]]*\](?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+ldr[ \t]+([^,]+), [^][\n]*(?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+ldr[ \t]+([^,]+), \[\1, \2\](?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+ldr[ \t]+([^,]+), \[(?:sp|fp)[^]]*\]\n[ \t]+ldr[ \t]+([^,]+), \[\3\](?:\n[ \t]+(?!ldr)\w[^\n]*)*\n[ \t]+cmp[ \t]+\4, \5(?:\n[ \t]+(?!cmp)\w[^\n]*)*\n[ \t]+bl[ \t]+__stack_chk_fail} } } */
|
||||
Loading…
Reference in New Issue