* config/mips/sr71k.md, config/mips/7000.md: Reformat.
From-SVN: r99591
This commit is contained in:
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@ -1,3 +1,7 @@
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2005-05-11 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/sr71k.md, config/mips/7000.md: Reformat.
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2005-05-11 Kazu Hirata <kazu@cs.umass.edu>
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PR tree-optimizer/18472
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@ -42,23 +42,23 @@
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(define_cpu_unit "ixum_addsub_agen" "rm7000_other")
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;; Integer execution unit (F-Pipe).
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(define_cpu_unit "ixuf_addsub" "rm7000_other")
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(define_cpu_unit "ixuf_branch" "rm7000_other")
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(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
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(define_cpu_unit "ixuf_addsub" "rm7000_other")
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(define_cpu_unit "ixuf_branch" "rm7000_other")
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(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
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(define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
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;; Floating-point unit (F-Pipe).
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(define_cpu_unit "fxuf_add" "rm7000_other")
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(define_cpu_unit "fxuf_mpy" "rm7000_other")
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(define_cpu_unit "fxuf_add" "rm7000_other")
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(define_cpu_unit "fxuf_mpy" "rm7000_other")
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(define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
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(define_cpu_unit "fxuf_divsqrt" "rm7000_other")
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(define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
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(exclusion_set "ixuf_addsub"
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"ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
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(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
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;; After branch any insn cannot be issued.
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(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
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@ -67,14 +67,14 @@
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;; Define reservations for unit name mnemonics or combinations.
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;;
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(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
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(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
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(define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
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(define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
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(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
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(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
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(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
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(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
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(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
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(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
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(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
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(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
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(define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
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(define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
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@ -87,123 +87,131 @@
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;;
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(define_insn_reservation "rm7_int_other" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
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"rm7_iaddsub")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
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"rm7_iaddsub")
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(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
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(eq_attr "type" "load,fpload,fpidxload"))
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"rm7_imem")
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(define_insn_reservation "rm7_ld" 2
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "load,fpload,fpidxload"))
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"rm7_imem")
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(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
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(eq_attr "type" "store,fpstore,fpidxstore"))
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"rm7_imem")
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(define_insn_reservation "rm7_st" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "store,fpstore,fpidxstore"))
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"rm7_imem")
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(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"rm7_impydiv+(rm7_impydiv_iter*36)")
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(define_insn_reservation "rm7_idiv_si" 36
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"rm7_impydiv+(rm7_impydiv_iter*36)")
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(define_insn_reservation "rm7_idiv_di" 68 (and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*68)")
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(define_insn_reservation "rm7_idiv_di" 68
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*68)")
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(define_insn_reservation "rm7_impy_si_mult" 5
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(and (eq_attr "mode" "SI")
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(match_operand 0 "hilo_operand"))))
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"rm7_impydiv+(rm7_impydiv_iter*3)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(and (eq_attr "mode" "SI")
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(match_operand 0 "hilo_operand"))))
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"rm7_impydiv+(rm7_impydiv_iter*3)")
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;; There are an additional 2 stall cycles.
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(define_insn_reservation "rm7_impy_si_mul" 2
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(and (eq_attr "mode" "SI")
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(not (match_operand 0 "hilo_operand")))))
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"rm7_impydiv")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3,imadd")
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(and (eq_attr "mode" "SI")
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(not (match_operand 0 "hilo_operand")))))
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"rm7_impydiv")
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(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*8)")
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(define_insn_reservation "rm7_impy_di" 9
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*8)")
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;; Move to/from HI/LO.
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(define_insn_reservation "rm7_mthilo" 3
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mthilo"))
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"rm7_impydiv")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mthilo"))
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"rm7_impydiv")
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(define_insn_reservation "rm7_mfhilo" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mfhilo"))
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"rm7_impydiv")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mfhilo"))
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"rm7_impydiv")
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;; Move to/from fp coprocessor.
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(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
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(eq_attr "type" "xfer"))
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"rm7_iaddsub")
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(define_insn_reservation "rm7_ixfer" 2
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "xfer"))
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"rm7_iaddsub")
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(define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
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(eq_attr "type" "branch,jump,call"))
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"rm7_branch")
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(define_insn_reservation "rm7_ibr" 3
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "branch,jump,call"))
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"rm7_branch")
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;;
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;; Describe instruction reservations for the floating-point operations.
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;;
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(define_insn_reservation "rm7_fp_quick" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fneg,fcmp,fabs,fmove"))
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"rm7_fpadd")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fneg,fcmp,fabs,fmove"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_other" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fadd"))
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"rm7_fpadd")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fadd"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_cvt" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fcvt"))
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"rm7_fpadd")
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fcvt"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_divsqrt_df" 36
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
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(define_insn_reservation "rm7_fp_divsqrt_sf" 21
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
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(define_insn_reservation "rm7_fp_rsqrt_df" 68
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
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(define_insn_reservation "rm7_fp_rsqrt_sf" 38
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
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(define_insn_reservation "rm7_fp_mpy_sf" 4
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"rm7_fpmpy+rm7_fpmpy_iter")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"rm7_fpmpy+rm7_fpmpy_iter")
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(define_insn_reservation "rm7_fp_mpy_df" 5
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"rm7_fpmpy+(rm7_fpmpy_iter*2)")
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"rm7_fpmpy+(rm7_fpmpy_iter*2)")
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;; Force single-dispatch for unknown or multi.
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(define_insn_reservation "rm7_unknown" 1 (and (eq_attr "cpu" "r7000")
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(eq_attr "type" "unknown,multi"))
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"rm7_single_dispatch")
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(define_insn_reservation "rm7_unknown" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "unknown,multi"))
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"rm7_single_dispatch")
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@ -124,150 +124,131 @@
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;;
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(define_insn_reservation "ir_sr70_unknown"
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1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "unknown"))
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"serial_dispatch")
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(define_insn_reservation "ir_sr70_unknown" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "unknown"))
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"serial_dispatch")
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;; Assume prediction fails.
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(define_insn_reservation "ir_sr70_branch"
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6
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "branch,jump,call"))
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"ri_branch")
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(define_insn_reservation "ir_sr70_branch" 6
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "branch,jump,call"))
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"ri_branch")
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(define_insn_reservation "ir_sr70_load"
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2
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "load"))
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"ri_mem")
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(define_insn_reservation "ir_sr70_load" 2
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "load"))
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"ri_mem")
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(define_insn_reservation "ir_sr70_store"
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1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "store"))
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"ri_mem")
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(define_insn_reservation "ir_sr70_store" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "store"))
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"ri_mem")
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;;
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;; float loads/stores flow through both cpu and cp1...
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;;
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(define_insn_reservation "ir_sr70_fload"
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9
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpload,fpidxload"))
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"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
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(define_insn_reservation "ir_sr70_fload" 9
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpload,fpidxload"))
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"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
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(define_insn_reservation "ir_sr70_fstore"
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1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpstore,fpidxstore"))
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"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
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(define_insn_reservation "ir_sr70_fstore" 1
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "fpstore,fpidxstore"))
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"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
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;; This reservation is for conditional move based on integer
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;; or floating point CC.
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(define_insn_reservation "ir_sr70_condmove"
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4
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "condmove"))
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"ri_insns")
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(define_insn_reservation "ir_sr70_condmove" 4
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(and (eq_attr "cpu" "sr71000")
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(eq_attr "type" "condmove"))
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"ri_insns")
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;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
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;; are different. Like float load/store, these insns use multiple
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;; resources simultaneously
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(define_insn_reservation "ir_sr70_xfer_from"
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6
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "xfer")
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(eq_attr "mode" "!SF,DF,FPSW")))
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"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
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(define_insn_reservation "ir_sr70_xfer_from" 6
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(and (eq_attr "cpu" "sr71000")
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(and (eq_attr "type" "xfer")
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(eq_attr "mode" "!SF,DF,FPSW")))
|
||||
"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_xfer_to"
|
||||
9
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "xfer")
|
||||
(eq_attr "mode" "SF,DF")))
|
||||
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
|
||||
(define_insn_reservation "ir_sr70_xfer_to" 9
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "xfer")
|
||||
(eq_attr "mode" "SF,DF")))
|
||||
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_hilo"
|
||||
1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "mthilo,mfhilo"))
|
||||
"ri_insns")
|
||||
(define_insn_reservation "ir_sr70_hilo" 1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "mthilo,mfhilo"))
|
||||
"ri_insns")
|
||||
|
||||
(define_insn_reservation "ir_sr70_arith"
|
||||
1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "arith,shift,slt,clz,const,trap"))
|
||||
"ri_insns")
|
||||
(define_insn_reservation "ir_sr70_arith" 1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "arith,shift,slt,clz,const,trap"))
|
||||
"ri_insns")
|
||||
|
||||
;; emulate repeat (dispatch stall) by spending extra cycle(s) in
|
||||
;; in iter unit
|
||||
(define_insn_reservation "ir_sr70_imul_si"
|
||||
4
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "imul,imul3,imadd")
|
||||
(eq_attr "mode" "SI")))
|
||||
"ri_alux,ipu_alux,ipu_macc_iter")
|
||||
(define_insn_reservation "ir_sr70_imul_si" 4
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "imul,imul3,imadd")
|
||||
(eq_attr "mode" "SI")))
|
||||
"ri_alux,ipu_alux,ipu_macc_iter")
|
||||
|
||||
(define_insn_reservation "ir_sr70_imul_di"
|
||||
6
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "imul,imul3,imadd")
|
||||
(eq_attr "mode" "DI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*3)")
|
||||
(define_insn_reservation "ir_sr70_imul_di" 6
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "imul,imul3,imadd")
|
||||
(eq_attr "mode" "DI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*3)")
|
||||
|
||||
;; Divide algorithm is early out with best latency of 7 pcycles.
|
||||
;; Use worst case for scheduling purposes.
|
||||
(define_insn_reservation "ir_sr70_idiv_si"
|
||||
41
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "SI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*38)")
|
||||
(define_insn_reservation "ir_sr70_idiv_si" 41
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "SI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*38)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_idiv_di"
|
||||
73
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "DI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*70)")
|
||||
(define_insn_reservation "ir_sr70_idiv_di" 73
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "DI")))
|
||||
"ri_alux,ipu_alux,(ipu_macc_iter*70)")
|
||||
|
||||
;; extra reservations of fpu_fpu are for repeat latency
|
||||
(define_insn_reservation "ir_sr70_fadd_sf"
|
||||
8
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fadd")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
(define_insn_reservation "ir_sr70_fadd_sf" 8
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fadd")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fadd_df"
|
||||
10
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fadd")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
(define_insn_reservation "ir_sr70_fadd_df" 10
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fadd")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
|
||||
;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
|
||||
;; with the sub or add.
|
||||
(define_insn_reservation "ir_sr70_fmul_sf"
|
||||
8
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fmul,fmadd")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
(define_insn_reservation "ir_sr70_fmul_sf" 8
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fmul,fmadd")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_insn,fpu_fpu")
|
||||
|
||||
;; tie up the fpu unit to emulate the balance for the "repeat
|
||||
;; rate" of 8 (2 are spent in the iss unit)
|
||||
(define_insn_reservation "ir_sr70_fmul_df"
|
||||
16
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fmul,fmadd")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_insn,fpu_fpu*6")
|
||||
(define_insn_reservation "ir_sr70_fmul_df" 16
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fmul,fmadd")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_insn,fpu_fpu*6")
|
||||
|
||||
|
||||
;; RECIP insn uses same type attr as div, and for SR3, has same
|
||||
@ -275,77 +256,66 @@
|
||||
;; 28 -- only way to fix this is to introduce new insn attrs.
|
||||
;; cycles spent in iter unit are designed to satisfy balance
|
||||
;; of "repeat" latency after insn uses up rf_multi1 reservation
|
||||
(define_insn_reservation "ir_sr70_fdiv_sf"
|
||||
60
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fdiv,frdiv")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*51)")
|
||||
(define_insn_reservation "ir_sr70_fdiv_sf" 60
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fdiv,frdiv")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*51)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fdiv_df"
|
||||
120
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fdiv,frdiv")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*109)")
|
||||
(define_insn_reservation "ir_sr70_fdiv_df" 120
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fdiv,frdiv")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*109)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fabs"
|
||||
4
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fabs,fneg,fmove"))
|
||||
"rf_insn,fpu_fpu")
|
||||
(define_insn_reservation "ir_sr70_fabs" 4
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fabs,fneg,fmove"))
|
||||
"rf_insn,fpu_fpu")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fcmp"
|
||||
10
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fcmp"))
|
||||
"rf_insn,fpu_fpu")
|
||||
(define_insn_reservation "ir_sr70_fcmp" 10
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fcmp"))
|
||||
"rf_insn,fpu_fpu")
|
||||
|
||||
;; "fcvt" type attribute covers a number of diff insns, most have the same
|
||||
;; latency descriptions, a few vary. We use the
|
||||
;; most common timing (which is also worst case).
|
||||
(define_insn_reservation "ir_sr70_fcvt"
|
||||
12
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fcvt"))
|
||||
"rf_insn,fpu_fpu*4")
|
||||
(define_insn_reservation "ir_sr70_fcvt" 12
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "fcvt"))
|
||||
"rf_insn,fpu_fpu*4")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fsqrt_sf"
|
||||
62
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*53)")
|
||||
(define_insn_reservation "ir_sr70_fsqrt_sf" 62
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*53)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_fsqrt_df"
|
||||
122
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*111)")
|
||||
(define_insn_reservation "ir_sr70_fsqrt_df" 122
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*111)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_frsqrt_sf"
|
||||
48
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*39)")
|
||||
(define_insn_reservation "ir_sr70_frsqrt_sf" 48
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(eq_attr "mode" "SF")))
|
||||
"rf_multi1+(fpu_iter*39)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_frsqrt_df"
|
||||
240
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*229)")
|
||||
(define_insn_reservation "ir_sr70_frsqrt_df" 240
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(eq_attr "mode" "DF")))
|
||||
"rf_multi1+(fpu_iter*229)")
|
||||
|
||||
(define_insn_reservation "ir_sr70_multi"
|
||||
1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "multi"))
|
||||
"serial_dispatch")
|
||||
(define_insn_reservation "ir_sr70_multi" 1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "multi"))
|
||||
"serial_dispatch")
|
||||
|
||||
(define_insn_reservation "ir_sr70_nop"
|
||||
1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "nop"))
|
||||
"ri_insns")
|
||||
(define_insn_reservation "ir_sr70_nop" 1
|
||||
(and (eq_attr "cpu" "sr71000")
|
||||
(eq_attr "type" "nop"))
|
||||
"ri_insns")
|
||||
|
Loading…
Reference in New Issue
Block a user