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@ -366,7 +366,7 @@ init_reload ()
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/* See if reg+reg is a valid (and offsettable) address. */
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tem = gen_rtx (PLUS, Pmode,
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tem = gen_rtx (PLUS, Pmode,
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gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
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gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM));
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/* This way, we make sure that reg+reg is an offsettable address. */
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@ -521,7 +521,7 @@ reload (first, global, dumpfile)
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/* Initialize the save area information for caller-save, in case some
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are needed. */
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init_save_areas ();
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/* Compute which hard registers are now in use
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as homes for pseudo registers.
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This is done here rather than (eg) in global_alloc
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@ -570,7 +570,7 @@ reload (first, global, dumpfile)
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rtx note = find_reg_note (insn, REG_EQUIV, 0);
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if (note
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#ifdef LEGITIMATE_PIC_OPERAND_P
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&& (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
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&& (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
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|| LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
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#endif
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)
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@ -647,7 +647,7 @@ reload (first, global, dumpfile)
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#endif
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/* Count the number of eliminable registers and build the FROM and TO
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REG rtx's. Note that code in gen_rtx will cause, e.g.,
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REG rtx's. Note that code in gen_rtx will cause, e.g.,
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gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
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We depend on this. */
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for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
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@ -839,7 +839,7 @@ reload (first, global, dumpfile)
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and constant, it is probably not addressable because the constant is
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out of range, in that case record the address; we will generate
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hairy code to compute the address in a register each time it is
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needed.
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needed.
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If the location is not addressable, but does not have one of the
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above forms, assign a stack slot. We have to do this to avoid the
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@ -868,7 +868,7 @@ reload (first, global, dumpfile)
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else
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{
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/* Make a new stack slot. Then indicate that something
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changed so we go back and recompute offsets for
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changed so we go back and recompute offsets for
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eliminable registers because the allocation of memory
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below might change some offset. reg_equiv_{mem,address}
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will be set up for this pseudo on the next pass around
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@ -879,7 +879,7 @@ reload (first, global, dumpfile)
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something_changed = 1;
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}
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}
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/* If we allocated another psuedo to the stack, redo elimination
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bookkeeping. */
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if (something_changed)
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@ -1024,7 +1024,7 @@ reload (first, global, dumpfile)
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}
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/* If this insn has no reloads, we need not do anything except
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in the case of a CALL_INSN when we have caller-saves and
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in the case of a CALL_INSN when we have caller-saves and
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caller-save needs reloads. */
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if (n_reloads == 0
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@ -1179,7 +1179,7 @@ reload (first, global, dumpfile)
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needed for this insn. However, the spill register
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can be used by any reload of this insn, so we only
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need do something if no need for that class has
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been recorded.
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been recorded.
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The assumption that every CALL_INSN will trigger a
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caller-save is highly conservative, however, the number
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@ -1279,7 +1279,7 @@ reload (first, global, dumpfile)
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supports the sum of two registers for an address; see
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find_address_reloads for details. */
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caller_save_spill_class
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caller_save_spill_class
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= double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
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caller_save_group_size
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= CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
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@ -1331,7 +1331,7 @@ reload (first, global, dumpfile)
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count_possible_groups (group_size, group_mode, max_groups);
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/* Now count all spill regs against the individual need,
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This includes those counted above for groups,
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This includes those counted above for groups,
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but not those previously counted for nongroups.
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Those that weren't counted_for_groups can also count against
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@ -1373,7 +1373,7 @@ reload (first, global, dumpfile)
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no longer replace register C with register B and we need to disable
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such an elimination, if it exists. This occurs often with A == ap,
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B == sp, and C == fp. */
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for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
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{
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struct elim_table *op;
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@ -1839,7 +1839,7 @@ count_possible_groups (group_size, group_mode, max_groups)
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p = reg_class_superclasses[i];
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while (*p != LIM_REG_CLASSES)
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max_groups[(int) *p++]--;
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/* Don't count these registers again. */
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/* Don't count these registers again. */
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for (k = 0; k < group_size[i]; k++)
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SET_HARD_REG_BIT (counted_for_groups, j + k);
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}
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@ -2171,7 +2171,7 @@ set_label_offsets (x, insn, initial_p)
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/* If neither of the above cases is true, compare each offset
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with those previously recorded and suppress any eliminations
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where the offsets disagree. */
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for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
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if (offsets_at[CODE_LABEL_NUMBER (x)][i]
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!= (initial_p ? reg_eliminate[i].initial_offset
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@ -2259,7 +2259,7 @@ set_label_offsets (x, insn, initial_p)
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static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
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/* Scan X and replace any eliminable registers (such as fp) with a
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/* Scan X and replace any eliminable registers (such as fp) with a
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replacement (such as sp), plus an offset.
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MEM_MODE is the mode of an enclosing MEM. We need this to know how
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@ -2401,7 +2401,7 @@ eliminate_regs (x, mem_mode, insn)
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if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
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{
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/* If one side is a PLUS and the other side is a pseudo that
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didn't get a hard register but has a reg_equiv_constant,
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didn't get a hard register but has a reg_equiv_constant,
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we must replace the constant here since it may no longer
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be in the position of any operand. */
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if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
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@ -2609,7 +2609,7 @@ eliminate_regs (x, mem_mode, insn)
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if (GET_CODE (SET_DEST (x)) == REG)
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{
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/* See if this is setting the replacement register for an
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elimination.
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elimination.
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If DEST is the frame pointer, we do nothing because we assume that
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all assignments to the frame pointer are for non-local gotos and
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@ -2819,7 +2819,7 @@ eliminate_regs_in_insn (insn, replace)
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REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, 0);
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val = 1;
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}
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/* Loop through all elimination pairs. See if any have changed and
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recalculate the number not at initial offset.
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@ -2937,7 +2937,7 @@ spill_hard_reg (regno, global, dumpfile, cant_eliminate)
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for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
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if (reg_renumber[i] >= 0
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&& reg_renumber[i] <= regno
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&& (reg_renumber[i]
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&& (reg_renumber[i]
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+ HARD_REGNO_NREGS (reg_renumber[i],
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PSEUDO_REGNO_MODE (i))
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> regno))
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@ -2960,7 +2960,7 @@ spill_hard_reg (regno, global, dumpfile, cant_eliminate)
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*p != LIM_REG_CLASSES; p++)
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if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
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break;
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if (*p == LIM_REG_CLASSES)
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continue;
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}
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@ -3278,7 +3278,7 @@ reload_as_needed (first, live_known)
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int class;
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/* If this block has not had spilling done for a
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particular class, deactivate any optional reloads
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particular class, deactivate any optional reloads
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of that class lest they try to use a spill-reg which isn't
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available here. If we have any non-optionals that need a
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spill reg, abort. */
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@ -3448,7 +3448,7 @@ reload_reg_class_lower (p1, p2)
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{
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register int r1 = *p1, r2 = *p2;
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register int t;
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/* Consider required reloads before optional ones. */
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t = reload_optional[r1] - reload_optional[r2];
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if (t != 0)
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@ -3703,7 +3703,7 @@ allocate_reload_reg (r, insn, last_reload, noerror)
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/* If we put this reload ahead, thinking it is a group,
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then insist on finding a group. Otherwise we can grab a
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reg that some other reload needs.
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reg that some other reload needs.
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(That can happen when we have a 68000 DATA_OR_FP_REG
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which is a group of data regs or one fp reg.)
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We need not be so restrictive if there are no more reloads
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@ -3948,7 +3948,7 @@ choose_reload_regs (insn, avoid_return_reg)
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#if 0 /* Not needed, now that we can always retry without inheritance. */
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/* See if we have more mandatory reloads than spill regs.
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If so, then we cannot risk optimizations that could prevent
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reloads from sharing one spill register.
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reloads from sharing one spill register.
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Since we will try finding a better register than reload_reg_rtx
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unless it is equal to reload_in or reload_out, count such reloads. */
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@ -3957,7 +3957,7 @@ choose_reload_regs (insn, avoid_return_reg)
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int tem = 0;
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#ifdef SMALL_REGISTER_CLASSES
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int tem = (avoid_return_reg != 0);
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#endif
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#endif
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for (j = 0; j < n_reloads; j++)
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if (! reload_optional[j]
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&& (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
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@ -3989,7 +3989,7 @@ choose_reload_regs (insn, avoid_return_reg)
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/* In order to be certain of getting the registers we need,
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we must sort the reloads into order of increasing register class.
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Then our grabbing of reload registers will parallel the process
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that provided the reload registers.
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that provided the reload registers.
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Also note whether any of the reloads wants a consecutive group of regs.
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If so, record the maximum size of the group desired and what
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@ -4544,7 +4544,7 @@ emit_reload_insns (insn)
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/* If OLDEQUIV is a spill register, don't use it for this
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if any other reload needs it at an earlier stage of this insn
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or at this stage. */
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or at this stage. */
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if (spill_reg_order[regno] >= 0
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&& (! reload_reg_free_p (regno, reload_when_needed[j])
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|| ! reload_reg_free_before_p (regno,
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@ -4719,10 +4719,10 @@ emit_reload_insns (insn)
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new_icode = reload_in_optab[(int) mode];
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if (new_icode != CODE_FOR_nothing
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&& ((insn_operand_predicate[(int) new_icode][0]
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&& ! (insn_operand_predicate[(int) new_icode][0]
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&& ! ((*insn_operand_predicate[(int) new_icode][0])
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(reloadreg, mode)))
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|| (insn_operand_predicate[(int) new_icode]
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&& ! (insn_operand_predicate[(int) new_icode][1]
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|| (insn_operand_predicate[(int) new_icode][1]
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&& ! ((*insn_operand_predicate[(int) new_icode][1])
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(oldequiv, mode)))))
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new_icode = CODE_FOR_nothing;
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@ -4860,7 +4860,7 @@ emit_reload_insns (insn)
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{
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register rtx reloadreg = reload_reg_rtx[j];
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#if 0
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#if 0
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/* We can't abort here because we need to support this for sched.c.
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It's not terrible to miss a REG_DEAD note, but we should try
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to figure out how to do this correctly. */
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@ -4900,7 +4900,7 @@ emit_reload_insns (insn)
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&& GET_CODE (reload_in[j]) == REG
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&& spill_reg_store[reload_spill_index[j]] == 0
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&& reload_inheritance_insn[j] != 0
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&& find_regno_note (reload_inheritance_insn[j], REG_DEAD,
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&& find_regno_note (reload_inheritance_insn[j], REG_DEAD,
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REGNO (reload_reg_rtx[j])))
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remove_death (REGNO (reload_reg_rtx[j]),
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reload_inheritance_insn[j]);
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@ -5258,7 +5258,7 @@ emit_reload_insns (insn)
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/* If there are two separate reloads (one in and one out)
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for the same (hard or pseudo) reg,
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leave reg_last_reload_reg set
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leave reg_last_reload_reg set
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based on the output reload.
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Otherwise, set it from this input reload. */
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if (!reg_has_output_reload[nregno]
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@ -5312,7 +5312,7 @@ gen_input_reload (reloadreg, in, before_insn)
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{
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register rtx prev_insn = PREV_INSN (before_insn);
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/* How to do this reload can get quite tricky. Normally, we are being
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/* How to do this reload can get quite tricky. Normally, we are being
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asked to reload a simple operand, such as a MEM, a constant, or a pseudo
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register that didn't get a hard register. In that case we can just
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call emit_move_insn.
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@ -5356,17 +5356,17 @@ gen_input_reload (reloadreg, in, before_insn)
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but we need to pass the insn as an operand to `recog' and it is
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simpler to emit and then delete the insn if not valid than to
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dummy things up. */
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rtx move_operand, other_operand, insn;
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int code;
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/* Since constraint checking is strict, commutativity won't be
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checked, so we need to do that here to avoid spurious failure
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if the add instruction is two-address and the second operand
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of the add is the same as the reload reg, which is frequently
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the case. If the insn would be A = B + A, rearrange it so
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it will be A = A + B as constrain_operands expects. */
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if (GET_CODE (XEXP (in, 1)) == REG
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&& REGNO (reloadreg) == REGNO (XEXP (in, 1)))
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in = gen_rtx (PLUS, GET_MODE (in), XEXP (in, 1), XEXP (in, 0));
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@ -5526,7 +5526,7 @@ delete_output_reload (insn, j, output_reload_insn)
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}
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/* Output reload-insns to reload VALUE into RELOADREG.
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/* Output reload-insns to reload VALUE into RELOADREG.
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VALUE is a autoincrement or autodecrement RTX whose operand
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is a register or memory location;
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so reloading involves incrementing that location.
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