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aarch64-simd.md (aarch64_combine<mode>): Directly call aarch64_split_simd_combine. 

2017-06-19  Michael Collison  <michael.collison@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly
	call aarch64_split_simd_combine.
	* (aarch64_combine_internal<mode>): Delete pattern.
	* config/aarch64/aarch64.c (aarch64_split_simd_combine):
	Allow register and subreg operands.

From-SVN: r249702
This commit is contained in:
Michael Collison 2017-06-27 17:29:06 +00:00 committed by Michael Collison
parent b2cf76f3a5
commit a977dc0c5e
3 changed files with 41 additions and 61 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2017-06-27 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly
call aarch64_split_simd_combine.
* (aarch64_combine_internal<mode>): Delete pattern.
* config/aarch64/aarch64.c (aarch64_split_simd_combine):
Allow register and subreg operands.
2017-06-27 Jerome Lambourg <lambourg@adacore.com>
* config/i386/vxworks.h (ASM_SPEC): Remove definition. No target

30
gcc/config/aarch64/aarch64-simd.md
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@ -2809,38 +2809,10 @@
(match_operand:VDC 2 "register_operand")]
"TARGET_SIMD"
{
rtx op1, op2;
if (BYTES_BIG_ENDIAN)
{
op1 = operands[2];
op2 = operands[1];
}
else
{
op1 = operands[1];
op2 = operands[2];
}
emit_insn (gen_aarch64_combine_internal<mode> (operands[0], op1, op2));
DONE;
}
)
aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
(define_insn_and_split "aarch64_combine_internal<mode>"
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
(vec_concat:<VDBL> (match_operand:VDC 1 "register_operand" "w")
(match_operand:VDC 2 "register_operand" "w")))]
"TARGET_SIMD"
"#"
"&& reload_completed"
[(const_int 0)]
{
if (BYTES_BIG_ENDIAN)
aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
else
aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
DONE;
}
[(set_attr "type" "multiple")]
)
(define_expand "aarch64_simd_combine<mode>"

64
gcc/config/aarch64/aarch64.c
View File

@ -1732,41 +1732,41 @@ aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2)
machine_mode dst_mode = GET_MODE (dst);
gcc_assert (VECTOR_MODE_P (dst_mode));
gcc_assert (register_operand (dst, dst_mode)
&& register_operand (src1, src_mode)
&& register_operand (src2, src_mode));
if (REG_P (dst) && REG_P (src1) && REG_P (src2))
rtx (*gen) (rtx, rtx, rtx);
switch (src_mode)
{
rtx (*gen) (rtx, rtx, rtx);
switch (src_mode)
{
case V8QImode:
gen = gen_aarch64_simd_combinev8qi;
break;
case V4HImode:
gen = gen_aarch64_simd_combinev4hi;
break;
case V2SImode:
gen = gen_aarch64_simd_combinev2si;
break;
case V4HFmode:
gen = gen_aarch64_simd_combinev4hf;
break;
case V2SFmode:
gen = gen_aarch64_simd_combinev2sf;
break;
case DImode:
gen = gen_aarch64_simd_combinedi;
break;
case DFmode:
gen = gen_aarch64_simd_combinedf;
break;
default:
gcc_unreachable ();
}
emit_insn (gen (dst, src1, src2));
return;
case V8QImode:
gen = gen_aarch64_simd_combinev8qi;
break;
case V4HImode:
gen = gen_aarch64_simd_combinev4hi;
break;
case V2SImode:
gen = gen_aarch64_simd_combinev2si;
break;
case V4HFmode:
gen = gen_aarch64_simd_combinev4hf;
break;
case V2SFmode:
gen = gen_aarch64_simd_combinev2sf;
break;
case DImode:
gen = gen_aarch64_simd_combinedi;
break;
case DFmode:
gen = gen_aarch64_simd_combinedf;
break;
default:
gcc_unreachable ();
}
emit_insn (gen (dst, src1, src2));
return;
}
/* Split a complex SIMD move. */