aarch64-simd.md (aarch64_combine<mode>): Directly call aarch64_split_simd_combine.
2017-06-19 Michael Collison <michael.collison@arm.com> * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly call aarch64_split_simd_combine. * (aarch64_combine_internal<mode>): Delete pattern. * config/aarch64/aarch64.c (aarch64_split_simd_combine): Allow register and subreg operands. From-SVN: r249702
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@ -1,3 +1,11 @@
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2017-06-27 Michael Collison <michael.collison@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly
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call aarch64_split_simd_combine.
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* (aarch64_combine_internal<mode>): Delete pattern.
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* config/aarch64/aarch64.c (aarch64_split_simd_combine):
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Allow register and subreg operands.
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2017-06-27 Jerome Lambourg <lambourg@adacore.com>
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* config/i386/vxworks.h (ASM_SPEC): Remove definition. No target
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@ -2809,38 +2809,10 @@
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(match_operand:VDC 2 "register_operand")]
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"TARGET_SIMD"
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{
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rtx op1, op2;
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if (BYTES_BIG_ENDIAN)
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{
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op1 = operands[2];
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op2 = operands[1];
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}
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else
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{
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op1 = operands[1];
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op2 = operands[2];
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}
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emit_insn (gen_aarch64_combine_internal<mode> (operands[0], op1, op2));
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DONE;
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}
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)
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aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
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(define_insn_and_split "aarch64_combine_internal<mode>"
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[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
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(vec_concat:<VDBL> (match_operand:VDC 1 "register_operand" "w")
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(match_operand:VDC 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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if (BYTES_BIG_ENDIAN)
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aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
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else
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aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
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DONE;
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}
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[(set_attr "type" "multiple")]
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)
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(define_expand "aarch64_simd_combine<mode>"
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@ -1732,41 +1732,41 @@ aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2)
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machine_mode dst_mode = GET_MODE (dst);
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gcc_assert (VECTOR_MODE_P (dst_mode));
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gcc_assert (register_operand (dst, dst_mode)
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&& register_operand (src1, src_mode)
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&& register_operand (src2, src_mode));
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if (REG_P (dst) && REG_P (src1) && REG_P (src2))
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rtx (*gen) (rtx, rtx, rtx);
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switch (src_mode)
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{
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rtx (*gen) (rtx, rtx, rtx);
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switch (src_mode)
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{
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case V8QImode:
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gen = gen_aarch64_simd_combinev8qi;
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break;
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case V4HImode:
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gen = gen_aarch64_simd_combinev4hi;
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break;
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case V2SImode:
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gen = gen_aarch64_simd_combinev2si;
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break;
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case V4HFmode:
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gen = gen_aarch64_simd_combinev4hf;
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break;
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case V2SFmode:
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gen = gen_aarch64_simd_combinev2sf;
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break;
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case DImode:
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gen = gen_aarch64_simd_combinedi;
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break;
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case DFmode:
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gen = gen_aarch64_simd_combinedf;
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen (dst, src1, src2));
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return;
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case V8QImode:
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gen = gen_aarch64_simd_combinev8qi;
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break;
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case V4HImode:
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gen = gen_aarch64_simd_combinev4hi;
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break;
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case V2SImode:
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gen = gen_aarch64_simd_combinev2si;
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break;
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case V4HFmode:
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gen = gen_aarch64_simd_combinev4hf;
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break;
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case V2SFmode:
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gen = gen_aarch64_simd_combinev2sf;
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break;
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case DImode:
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gen = gen_aarch64_simd_combinedi;
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break;
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case DFmode:
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gen = gen_aarch64_simd_combinedf;
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break;
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default:
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gcc_unreachable ();
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}
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emit_insn (gen (dst, src1, src2));
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return;
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}
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/* Split a complex SIMD move. */
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