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Fix v850 ICE.

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* combine.c (try_combine): When split an instruction pair, where the
	first has a sign_extend src, verify that the src and dest modes match.

From-SVN: r57371
This commit is contained in:
Jim Wilson 2002-09-20 21:42:25 +00:00 committed by Jim Wilson
parent 27eba30922
commit a9b2f05974
2 changed files with 11 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2002-09-20 Jim Wilson <wilson@redhat.com>
* combine.c (try_combine): When split an instruction pair, where the
first has a sign_extend src, verify that the src and dest modes match.
2002-09-20 Richard Henderson <rth@redhat.com>
* config/mips/mips.c (dfhigh, dflow, sfhigh, sflow): Remove.

6
gcc/combine.c
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@ -2316,6 +2316,10 @@ try_combine (i3, i2, i1, new_direct_jump_p)
copy. This saves at least one insn, more if register allocation can
eliminate the copy.
We cannot do this if the destination of the first assignment is a
condition code register or cc0. We eliminate this case by making sure
the SET_DEST and SET_SRC have the same mode.
We cannot do this if the destination of the second assignment is
a register that we have already assumed is zero-extended. Similarly
for a SUBREG of such a register. */
@ -2325,6 +2329,8 @@ try_combine (i3, i2, i1, new_direct_jump_p)
&& XVECLEN (newpat, 0) == 2
&& GET_CODE (XVECEXP (newpat, 0, 0)) == SET
&& GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
&& (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
== GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
&& GET_CODE (XVECEXP (newpat, 0, 1)) == SET
&& rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))