Add TIGERLAKE and COOPERLAKE to GCC.
2019-08-20 Lili Cui <lili.cui@intel.com> gcc/ * common/config/i386/i386-common.c (processor_names): Add tigerlake and cooperlake. (processor_alias_table): Add tigerlake and cooperlake. * config.gcc: Add -march=tigerlake and cooperlake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect tigerlake and cooperlake. Add "has_avx" to classify processor. * config/i386/i386-builtins.c (processor_model): Add M_INTEL_COREI7_TIGERLAKE and M_INTEL_COREI7_COOPERLAKE. (arch_names_table): Add tigerlake and cooperlake. (get_builtin_code_for_version) : Handle PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE. * config/i386/i386-c.c (ix86_target_macros_internal): Handle tigerlake and cooperlake. * config/i386/i386-options.c (m_TIGERLAKE) : Define. (m_COOPERLAKE) : Ditto. (m_CORE_AVX512): Ditto. (processor_cost_table): Add cascadelake. (ix86_option_override_internal): Hadle PTA_MOVDIRI, PTA_MOVDIR64B. * config/i386/i386.h (ix86_size_cost) : Define TARGET_TIGERLAKE and TARGET_COOPERLAKE. (processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE. (PTA_MOVDIRI): Ditto. (PTA_MOVDIR64B): Ditto. (PTA_COOPERLAKE) : Ditto. (PTA_TIGERLAKE) : Ditto. (processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE. * doc/extend.texi: Add tigerlake and cooperlake. * doc/invoke.texi: Add tigerlake and cooperlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march libgcc/ * config/i386/cpuinfo.h: Add INTEL_COREI7_TIGERLAKE and INTEL_COREI7_COOPERLAKE. From-SVN: r274693
This commit is contained in:
Hongtao Liu
parent
607a71e842
commit
a9fcfec30f
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@ -1,3 +1,36 @@
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2019-08-20 Lili Cui <lili.cui@intel.com>
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* common/config/i386/i386-common.c
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(processor_names): Add tigerlake and cooperlake.
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(processor_alias_table): Add tigerlake and cooperlake.
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* config.gcc: Add -march=tigerlake and cooperlake.
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* config/i386/driver-i386.c
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(host_detect_local_cpu): Detect tigerlake and cooperlake.
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Add "has_avx" to classify processor.
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* config/i386/i386-builtins.c (processor_model) :
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Add M_INTEL_COREI7_TIGERLAKE and M_INTEL_COREI7_COOPERLAKE.
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(arch_names_table): Add tigerlake and cooperlake.
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(get_builtin_code_for_version) : Handle PROCESSOR_TIGERLAKE
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and PROCESSOR_COOPERLAKE.
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* config/i386/i386-c.c
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(ix86_target_macros_internal): Handle tigerlake and cooperlake.
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* config/i386/i386-options.c
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(m_TIGERLAKE) : Define.
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(m_COOPERLAKE) : Ditto.
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(m_CORE_AVX512): Ditto.
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(processor_cost_table): Add cascadelake.
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(ix86_option_override_internal): Hadle PTA_MOVDIRI, PTA_MOVDIR64B.
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* config/i386/i386.h
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(ix86_size_cost) : Define TARGET_TIGERLAKE and TARGET_COOPERLAKE.
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(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
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(PTA_MOVDIRI): Ditto.
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(PTA_MOVDIR64B): Ditto.
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(PTA_COOPERLAKE) : Ditto.
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(PTA_TIGERLAKE) : Ditto.
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(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
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* doc/extend.texi: Add tigerlake and cooperlake.
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* doc/invoke.texi: Add tigerlake and cooperlake.
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2019-08-20 Gerald Pfeifer <gerald@pfeifer.com>
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* doc/install.texi (Specific, alpha): Remove note to use
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@ -1566,6 +1566,8 @@ const char *const processor_names[] =
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"icelake-client",
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"icelake-server",
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"cascadelake",
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"tigerlake",
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"cooperlake",
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"intel",
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"geode",
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"k6",
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@ -1648,6 +1650,8 @@ const pta processor_alias_table[] =
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PTA_ICELAKE_SERVER},
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{"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
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PTA_CASCADELAKE},
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{"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
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{"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
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{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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@ -664,7 +664,8 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \
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opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
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slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
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silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
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skylake goldmont goldmont-plus tremont cascadelake x86-64 native"
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skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake x86-64 \
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native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -863,36 +863,45 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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if (arch)
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{
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/* This is unknown family 0x6 CPU. */
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/* Assume Ice Lake Server. */
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if (has_wbnoinvd)
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cpu = "icelake-server";
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/* Assume Ice Lake. */
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else if (has_gfni)
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cpu = "icelake-client";
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/* Assume Cannon Lake. */
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else if (has_avx512vbmi)
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cpu = "cannonlake";
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/* Assume Knights Mill. */
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else if (has_avx5124vnniw)
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cpu = "knm";
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/* Assume Knights Landing. */
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else if (has_avx512er)
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cpu = "knl";
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/* Assume Skylake with AVX-512. */
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else if (has_avx512f)
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cpu = "skylake-avx512";
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/* Assume Skylake. */
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else if (has_clflushopt)
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cpu = "skylake";
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/* Assume Broadwell. */
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else if (has_adx)
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cpu = "broadwell";
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else if (has_avx2)
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if (has_avx)
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{
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/* Assume Tiger Lake */
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if (has_avx512vp2intersect)
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cpu = "tigerlake";
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/* Assume Cooper Lake */
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else if (has_avx512bf16)
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cpu = "cooperlake";
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/* Assume Ice Lake Server. */
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else if (has_wbnoinvd)
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cpu = "icelake-server";
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/* Assume Ice Lake. */
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else if (has_avx512bitalg)
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cpu = "icelake-client";
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/* Assume Cannon Lake. */
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else if (has_avx512vbmi)
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cpu = "cannonlake";
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/* Assume Knights Mill. */
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else if (has_avx5124vnniw)
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cpu = "knm";
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/* Assume Knights Landing. */
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else if (has_avx512er)
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cpu = "knl";
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/* Assume Skylake with AVX-512. */
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else if (has_avx512f)
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cpu = "skylake-avx512";
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/* Assume Skylake. */
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else if (has_clflushopt)
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cpu = "skylake";
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/* Assume Broadwell. */
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else if (has_adx)
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cpu = "broadwell";
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else if (has_avx2)
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/* Assume Haswell. */
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cpu = "haswell";
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else if (has_avx)
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cpu = "haswell";
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else
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/* Assume Sandy Bridge. */
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cpu = "sandybridge";
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cpu = "sandybridge";
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}
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else if (has_sse4_2)
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{
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if (has_gfni)
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@ -1972,7 +1972,9 @@ enum processor_model
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M_INTEL_COREI7_ICELAKE_CLIENT,
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M_INTEL_COREI7_ICELAKE_SERVER,
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M_AMDFAM17H_ZNVER2,
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M_INTEL_COREI7_CASCADELAKE
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M_INTEL_COREI7_CASCADELAKE,
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M_INTEL_COREI7_TIGERLAKE,
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M_INTEL_COREI7_COOPERLAKE
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};
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struct _arch_names_table
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@ -2001,6 +2003,8 @@ static const _arch_names_table arch_names_table[] =
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{"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
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{"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
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{"cascadelake", M_INTEL_COREI7_CASCADELAKE},
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{"tigerlake", M_INTEL_COREI7_TIGERLAKE},
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{"cooperlake", M_INTEL_COREI7_COOPERLAKE},
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"goldmont", M_INTEL_GOLDMONT},
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@ -2194,6 +2198,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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arg_str = "cascadelake";
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priority = P_PROC_AVX512F;
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break;
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case PROCESSOR_TIGERLAKE:
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arg_str = "tigerlake";
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priority = P_PROC_AVX512F;
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break;
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case PROCESSOR_COOPERLAKE:
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arg_str = "cooperlake";
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priority = P_PROC_AVX512F;
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break;
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case PROCESSOR_BONNELL:
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arg_str = "bonnell";
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priority = P_PROC_SSSE3;
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@ -222,6 +222,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__cascadelake");
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def_or_undef (parse_in, "__cascadelake__");
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break;
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case PROCESSOR_TIGERLAKE:
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def_or_undef (parse_in, "__tigerlake");
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def_or_undef (parse_in, "__tigerlake__");
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break;
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case PROCESSOR_COOPERLAKE:
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def_or_undef (parse_in, "__cooperlake");
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def_or_undef (parse_in, "__cooperlake__");
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/* use PROCESSOR_max to not set/unset the arch macro. */
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case PROCESSOR_max:
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break;
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@ -370,6 +377,12 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_CASCADELAKE:
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def_or_undef (parse_in, "__tune_cascadelake__");
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break;
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case PROCESSOR_TIGERLAKE:
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def_or_undef (parse_in, "__tune_tigerlake__");
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break;
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case PROCESSOR_COOPERLAKE:
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def_or_undef (parse_in, "__tune_cooperlake__");
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break;
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case PROCESSOR_INTEL:
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case PROCESSOR_GENERIC:
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break;
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@ -121,8 +121,11 @@ along with GCC; see the file COPYING3. If not see
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#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
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#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
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#define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE)
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#define m_TIGERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_TIGERLAKE)
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#define m_COOPERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_COOPERLAKE)
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#define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
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| m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE)
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| m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
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| m_TIGERLAKE | m_COOPERLAKE)
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#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
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#define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2)
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#define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
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@ -627,6 +630,8 @@ static const struct processor_costs *processor_cost_table[] =
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&skylake_cost,
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&skylake_cost,
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&skylake_cost,
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&skylake_cost,
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&skylake_cost,
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&intel_cost,
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&geode_cost,
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&k6_cost,
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@ -2049,6 +2054,12 @@ ix86_option_override_internal (bool main_args_p,
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&& !(opts->x_ix86_isa_flags2_explicit
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& OPTION_MASK_ISA_AVX512BF16))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BF16;
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if (((processor_alias_table[i].flags & PTA_MOVDIRI) != 0)
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVDIRI))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI;
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if (((processor_alias_table[i].flags & PTA_MOVDIR64B) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVDIR64B))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B;
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if (((processor_alias_table[i].flags & PTA_SGX) != 0)
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&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
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opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
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@ -440,6 +440,8 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
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#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
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#define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE)
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#define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE)
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#define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE)
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#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
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#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
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#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
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@ -2303,6 +2305,8 @@ enum processor_type
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PROCESSOR_ICELAKE_CLIENT,
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PROCESSOR_ICELAKE_SERVER,
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PROCESSOR_CASCADELAKE,
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PROCESSOR_TIGERLAKE,
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PROCESSOR_COOPERLAKE,
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PROCESSOR_INTEL,
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PROCESSOR_GEODE,
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PROCESSOR_K6,
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@ -2402,6 +2406,8 @@ const wide_int_bitmask PTA_AVX512VP2INTERSECT (0, HOST_WIDE_INT_1U << 9);
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const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
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const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10);
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const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11);
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const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
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const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
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const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
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| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
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@ -2422,6 +2428,7 @@ const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
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| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
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| PTA_CLWB;
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const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI;
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const wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
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const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
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| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
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| PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
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@ -2430,6 +2437,8 @@ const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
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| PTA_RDPID | PTA_CLWB;
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const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
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| PTA_WBNOINVD;
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const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
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| PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT;
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const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
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| PTA_AVX512F | PTA_AVX512CD;
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const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
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@ -21489,6 +21489,12 @@ Intel Core i7 Ice Lake Server CPU.
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@item cascadelake
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Intel Core i7 Cascadelake CPU.
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@item tigerlake
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Intel Core i7 Tigerlake CPU.
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@item cooperlake
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Intel Core i7 Cooperlake CPU.
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@item bonnell
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Intel Atom Bonnell CPU.
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|
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@ -27559,6 +27559,22 @@ SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
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BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
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AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
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@item cooperlake
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Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
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SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
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BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
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AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
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set support.
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@item tigerlake
|
||||
Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
|
||||
SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
|
||||
BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
|
||||
AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
|
||||
RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
|
||||
VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and AVX512VP2INTERSECT instruction
|
||||
set support.
|
||||
|
||||
@item k6
|
||||
AMD K6 CPU with MMX instruction set support.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2019-08-20 Lili Cui <lili.cui@intel.com>
|
||||
|
||||
* gcc.target/i386/funcspec-56.inc: Handle new march.
|
||||
* g++.target/i386/mv16.C: Handle new march
|
||||
|
||||
2019-08-20 Bernd Edlinger <bernd.edlinger@hotmail.de>
|
||||
|
||||
PR middle-end/89544
|
||||
|
|
|
|||
|
|
@ -72,6 +72,14 @@ int __attribute__ ((target("arch=cascadelake"))) foo () {
|
|||
return 19;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=tigerlake"))) foo () {
|
||||
return 20;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=cooperlake"))) foo () {
|
||||
return 21;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int val = foo ();
|
||||
|
|
@ -100,6 +108,10 @@ int main ()
|
|||
assert (val == 18);
|
||||
else if (__builtin_cpu_is ("cascadelake"))
|
||||
assert (val == 19);
|
||||
else if (__builtin_cpu_is ("tigerlake"))
|
||||
assert (val == 20);
|
||||
else if (__builtin_cpu_is ("cooperlake"))
|
||||
assert (val == 21);
|
||||
else
|
||||
assert (val == 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -151,6 +151,8 @@ extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonl
|
|||
extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client")));
|
||||
extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server")));
|
||||
extern void test_arch_cascadelake (void) __attribute__((__target__("arch=cascadelake")));
|
||||
extern void test_arch_tigerlake (void) __attribute__((__target__("arch=tigerlake")));
|
||||
extern void test_arch_cooperlake (void) __attribute__((__target__("arch=cooperlake")));
|
||||
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
|
||||
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
|
||||
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2019-08-20 Lili Cui <lilicui@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.h: Add INTEL_COREI7_TIGERLAKE and
|
||||
INTEL_COREI7_COOPERLAKE.
|
||||
|
||||
2019-07-31 Matt Thomas <matt@3am-software.com>
|
||||
Nick Hudson <nick@nthcliff.demon.co.uk>
|
||||
Matthew Green <mrg@eterna.com.au>
|
||||
|
|
|
|||
|
|
@ -77,6 +77,8 @@ enum processor_subtypes
|
|||
INTEL_COREI7_ICELAKE_SERVER,
|
||||
AMDFAM17H_ZNVER2,
|
||||
INTEL_COREI7_CASCADELAKE,
|
||||
INTEL_COREI7_TIGERLAKE,
|
||||
INTEL_COREI7_COOPERLAKE,
|
||||
CPU_SUBTYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue