OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Add new options: -mext-perf, -mext-perf2, -mext-string.

Browse Source 
gcc/
	* config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string.
	* config/nds32/nds32.opt: Refine the layout.
	* config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2,
	TARGET_EXT_STRING): Support new options.
	* config/nds32/nds32.h: Likewise.
	* config/nds32/nds32.md: Likewise.
	* config/nds32/nds32-predicates.c: Likewise.
	* config/nds32/constraints.md: Likewise.
	* common/config/nds32/nds32-common.c: Likewise.

Co-Authored-By: Kito Cheng <kito.cheng@gmail.com>

From-SVN: r254798
This commit is contained in:
Chung-Ju Wu 2017-11-16 09:15:21 +00:00 committed by Chung-Ju Wu
parent bde4b3ddd6
commit aa4b851ca2
8 changed files with 79 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2017-11-16 Chung-Ju Wu <jasonwucj@gmail.com>
Kito Cheng <kito.cheng@gmail.com>
* config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string.
* config/nds32/nds32.opt: Refine the layout.
* config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2,
TARGET_EXT_STRING): Support new options.
* config/nds32/nds32.h: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/constraints.md: Likewise.
* common/config/nds32/nds32-common.c: Likewise.
2017-11-16 Julia Koval <julia.koval@intel.com>
PR target/82983

12
gcc/common/config/nds32/nds32-common.c
View File

@ -97,14 +97,18 @@ static const struct default_options nds32_option_optimization_table[] =
Other MASK_XXX flags are set individually.
By default we enable
TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
TARGET_PERF_EXT : Generate performance extention instrcution.
TARGET_CMOV : Generate conditional move instruction. */
TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
TARGET_EXT_PERF : Generate performance extention instrcution.
TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
TARGET_EXT_STRING : Generate string extention instrcution.
TARGET_CMOV : Generate conditional move instruction. */
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
(TARGET_CPU_DEFAULT \
| MASK_16_BIT \
| MASK_PERF_EXT \
| MASK_EXT_PERF \
| MASK_EXT_PERF2 \
| MASK_EXT_STRING \
| MASK_CMOV)
#undef TARGET_HANDLE_OPTION

4
gcc/config/nds32/constraints.md
View File

@ -213,12 +213,12 @@
(define_constraint "Ixls"
"The immediate value 0x01"
(and (match_code "const_int")
(match_test "TARGET_PERF_EXT && (ival == 0x1)")))
(match_test "TARGET_EXT_PERF && (ival == 0x1)")))
(define_constraint "Ix11"
"The immediate value 0x7ff"
(and (match_code "const_int")
(match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
(match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
(define_constraint "Ibms"
"The immediate value with power of 2"

6
gcc/config/nds32/nds32-predicates.c
View File

@ -335,7 +335,7 @@ nds32_can_use_bclr_p (int ival)
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
/* 'bclr' is a performance extension instruction. */
return (TARGET_PERF_EXT && (one_bit_count == 1));
return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'bset' instruction can be used with IVAL. */
@ -350,7 +350,7 @@ nds32_can_use_bset_p (int ival)
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
/* 'bset' is a performance extension instruction. */
return (TARGET_PERF_EXT && (one_bit_count == 1));
return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'btgl' instruction can be used with IVAL. */
@ -365,7 +365,7 @@ nds32_can_use_btgl_p (int ival)
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
/* 'btgl' is a performance extension instruction. */
return (TARGET_PERF_EXT && (one_bit_count == 1));
return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'bitci' instruction can be used with IVAL. */

16
gcc/config/nds32/nds32.c
View File

@ -2188,8 +2188,14 @@ nds32_asm_file_start (void)
((TARGET_CMOV) ? "Yes"
: "No"));
fprintf (asm_out_file, "\t! Use performance extension\t: %s\n",
((TARGET_PERF_EXT) ? "Yes"
((TARGET_EXT_PERF) ? "Yes"
: "No"));
fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n",
((TARGET_EXT_PERF2) ? "Yes"
: "No"));
fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n",
((TARGET_EXT_STRING) ? "Yes"
: "No"));
fprintf (asm_out_file, "\t! ------------------------------------\n");
@ -2676,8 +2682,12 @@ nds32_option_override (void)
{
/* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
target_flags |= MASK_REDUCED_REGS;
/* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT. */
target_flags &= ~MASK_PERF_EXT;
/* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
target_flags &= ~MASK_EXT_PERF;
/* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
target_flags &= ~MASK_EXT_PERF2;
/* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
target_flags &= ~MASK_EXT_STRING;
}
/* See if we are using reduced-set registers:

8
gcc/config/nds32/nds32.h
View File

@ -448,8 +448,12 @@ enum nds32_builtins
builtin_define ("__NDS32_REDUCED_REGS__"); \
if (TARGET_CMOV) \
builtin_define ("__NDS32_CMOV__"); \
if (TARGET_PERF_EXT) \
builtin_define ("__NDS32_PERF_EXT__"); \
if (TARGET_EXT_PERF) \
builtin_define ("__NDS32_EXT_PERF__"); \
if (TARGET_EXT_PERF2) \
builtin_define ("__NDS32_EXT_PERF2__"); \
if (TARGET_EXT_STRING) \
builtin_define ("__NDS32_EXT_STRING__"); \
if (TARGET_16_BIT) \
builtin_define ("__NDS32_16_BIT__"); \
if (TARGET_GP_DIRECT) \

8
gcc/config/nds32/nds32.md
View File

@ -2336,7 +2336,7 @@ create_template:
(define_insn "clzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz:SI (match_operand:SI 1 "register_operand" " r")))]
"TARGET_PERF_EXT"
"TARGET_EXT_PERF"
"clz\t%0, %1"
[(set_attr "type" "alu")
(set_attr "length" "4")])
@ -2345,7 +2345,7 @@ create_template:
[(set (match_operand:SI 0 "register_operand" "=r")
(smax:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_PERF_EXT"
"TARGET_EXT_PERF"
"max\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])
@ -2354,7 +2354,7 @@ create_template:
[(set (match_operand:SI 0 "register_operand" "=r")
(smin:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_PERF_EXT"
"TARGET_EXT_PERF"
"min\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])
@ -2364,7 +2364,7 @@ create_template:
(zero_extract:SI (match_operand:SI 1 "register_operand" " r")
(const_int 1)
(match_operand:SI 2 "immediate_operand" " Iu05")))]
"TARGET_PERF_EXT"
"TARGET_EXT_PERF"
"btst\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])

36
gcc/config/nds32/nds32.opt
View File

@ -21,14 +21,19 @@
HeaderInclude
config/nds32/nds32-opts.h
mbig-endian
Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
; ---------------------------------------------------------------
; The following options are designed for aliasing and compatibility options.
EB
Target RejectNegative Alias(mbig-endian)
Generate code in big-endian mode.
mlittle-endian
Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
EL
Target RejectNegative Alias(mlittle-endian)
Generate code in little-endian mode.
; ---------------------------------------------------------------
mreduced-regs
Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation.
@ -37,14 +42,33 @@ mfull-regs
Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation.
; ---------------------------------------------------------------
mbig-endian
Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
Generate code in big-endian mode.
mlittle-endian
Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
Generate code in little-endian mode.
mcmov
Target Report Mask(CMOV)
Generate conditional move instructions.
mperf-ext
Target Report Mask(PERF_EXT)
mext-perf
Target Report Mask(EXT_PERF)
Generate performance extension instructions.
mext-perf2
Target Report Mask(EXT_PERF2)
Generate performance extension version 2 instructions.
mext-string
Target Report Mask(EXT_STRING)
Generate string extension instructions.
mv3push
Target Report Mask(V3PUSH)
Generate v3 push25/pop25 instructions.