mips-cpus.def: Add definition for p5600.
2014-06-05 Jaydeep Patil <Jaydeep.Patil@imgtec.com> Prachi Godbole <Prachi.Godbole@imgtec.com> * config/mips/mips-cpus.def: Add definition for p5600. Updated mips32r5 entry to use PROCESSOR_P5600. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips-protos.h (mips_fmadd_bypass): Add prototype. * config/mips/mips.c (mips_fmadd_bypass): New function. (mips_rtx_cost_data): Add costs for p5600. (mips_issue_rate): Add support for p5600. (mips_multipass_dfa_lookahead): Likewise. * config/mips/mips.h (TUNE_P5600): New define. (TUNE_MACC_CHAINS): Add TUNE_P5600. (MIPS_ISA_LEVEL_SPEC): Map -march=p5600 to -mips32r5. * config/mips/mips.md: Include p5600.md. (processor): Add p5600. * config/mips/p5600.md: New file. Co-Authored-By: Prachi Godbole <prachi.godbole@imgtec.com> From-SVN: r211265
This commit is contained in:
Jaydeep Patil
Andrew Bennett
parent
edbb074909
commit
aaaa9efcb4
@ -1,3 +1,21 @@
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2014-06-05 Jaydeep Patil <Jaydeep.Patil@imgtec.com>
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Prachi Godbole <Prachi.Godbole@imgtec.com>
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* config/mips/mips-cpus.def: Add definition for p5600. Updated
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mips32r5 entry to use PROCESSOR_P5600.
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* config/mips/mips-tables.opt: Regenerate.
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* config/mips/mips-protos.h (mips_fmadd_bypass): Add prototype.
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* config/mips/mips.c (mips_fmadd_bypass): New function.
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(mips_rtx_cost_data): Add costs for p5600.
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(mips_issue_rate): Add support for p5600.
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(mips_multipass_dfa_lookahead): Likewise.
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* config/mips/mips.h (TUNE_P5600): New define.
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(TUNE_MACC_CHAINS): Add TUNE_P5600.
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(MIPS_ISA_LEVEL_SPEC): Map -march=p5600 to -mips32r5.
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* config/mips/mips.md: Include p5600.md.
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(processor): Add p5600.
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* config/mips/p5600.md: New file.
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2014-06-05 Evgeny Stupachenko <evstupac@gmail.com>
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* config/i386/sse.md (*ssse3_palignr<mode>_perm): New.
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@ -49,7 +49,7 @@ MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY)
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for this yet, so in the short term we will use the same processor entry
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as mips32r2. */
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MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r5", PROCESSOR_74KF2_1, 36, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
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/* ??? For now just tune the generic MIPS64r2 and above for 5KC as well. */
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MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
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@ -145,6 +145,9 @@ MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
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MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0)
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MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
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/* MIPS32 Release 5 processors. */
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MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
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/* MIPS64 processors. */
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MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0)
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MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0)
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@ -315,6 +315,7 @@ extern bool mips16e_save_restore_pattern_p (rtx, HOST_WIDE_INT,
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extern bool mask_low_and_shift_p (enum machine_mode, rtx, rtx, int);
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extern int mask_low_and_shift_len (enum machine_mode, rtx, rtx);
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extern bool and_operands_ok (enum machine_mode, rtx, rtx);
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extern bool mips_fmadd_bypass (rtx, rtx);
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union mips_gen_fn_ptrs
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{
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@ -619,50 +619,53 @@ EnumValue
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Enum(mips_arch_opt_value) String(r1004kf1_1) Value(82)
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EnumValue
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Enum(mips_arch_opt_value) String(5kc) Value(83) Canonical
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Enum(mips_arch_opt_value) String(p5600) Value(83) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(r5kc) Value(83)
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Enum(mips_arch_opt_value) String(5kc) Value(84) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(5kf) Value(84) Canonical
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Enum(mips_arch_opt_value) String(r5kc) Value(84)
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EnumValue
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Enum(mips_arch_opt_value) String(r5kf) Value(84)
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Enum(mips_arch_opt_value) String(5kf) Value(85) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(20kc) Value(85) Canonical
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Enum(mips_arch_opt_value) String(r5kf) Value(85)
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EnumValue
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Enum(mips_arch_opt_value) String(r20kc) Value(85)
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Enum(mips_arch_opt_value) String(20kc) Value(86) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(sb1) Value(86) Canonical
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Enum(mips_arch_opt_value) String(r20kc) Value(86)
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EnumValue
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Enum(mips_arch_opt_value) String(sb1a) Value(87) Canonical
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Enum(mips_arch_opt_value) String(sb1) Value(87) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(sr71000) Value(88) Canonical
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Enum(mips_arch_opt_value) String(sb1a) Value(88) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(sr71k) Value(88)
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Enum(mips_arch_opt_value) String(sr71000) Value(89) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(xlr) Value(89) Canonical
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Enum(mips_arch_opt_value) String(sr71k) Value(89)
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EnumValue
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Enum(mips_arch_opt_value) String(loongson3a) Value(90) Canonical
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Enum(mips_arch_opt_value) String(xlr) Value(90) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(octeon) Value(91) Canonical
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Enum(mips_arch_opt_value) String(loongson3a) Value(91) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(octeon+) Value(92) Canonical
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Enum(mips_arch_opt_value) String(octeon) Value(92) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(octeon2) Value(93) Canonical
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Enum(mips_arch_opt_value) String(octeon+) Value(93) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(xlp) Value(94) Canonical
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Enum(mips_arch_opt_value) String(octeon2) Value(94) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(xlp) Value(95) Canonical
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@ -1180,6 +1180,19 @@ static const struct mips_rtx_cost_data
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COSTS_N_INSNS (68), /* int_div_di */
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* P5600 */
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COSTS_N_INSNS (4), /* fp_add */
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COSTS_N_INSNS (5), /* fp_mult_sf */
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COSTS_N_INSNS (5), /* fp_mult_df */
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COSTS_N_INSNS (17), /* fp_div_sf */
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COSTS_N_INSNS (17), /* fp_div_df */
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COSTS_N_INSNS (5), /* int_mult_si */
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COSTS_N_INSNS (5), /* int_mult_di */
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COSTS_N_INSNS (8), /* int_div_si */
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COSTS_N_INSNS (8), /* int_div_di */
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2, /* branch_cost */
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10 /* memory_latency */
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}
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};
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@ -13073,6 +13086,31 @@ mips_output_division (const char *division, rtx *operands)
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return s;
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}
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/* Return true if destination of IN_INSN is used as add source in
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OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
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madd.s dst, x, y, z
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madd.s a, dst, b, c */
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bool
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mips_fmadd_bypass (rtx out_insn, rtx in_insn)
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{
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int dst_reg, src_reg;
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gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
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gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
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extract_insn (in_insn);
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dst_reg = REG_P (recog_data.operand[0]);
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extract_insn (out_insn);
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src_reg = REG_P (recog_data.operand[1]);
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if (dst_reg == src_reg)
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return true;
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return false;
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}
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/* Return true if IN_INSN is a multiply-add or multiply-subtract
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instruction and if OUT_INSN assigns to the accumulator operand. */
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@ -13208,6 +13246,7 @@ mips_issue_rate (void)
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case PROCESSOR_LOONGSON_2E:
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case PROCESSOR_LOONGSON_2F:
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case PROCESSOR_LOONGSON_3A:
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case PROCESSOR_P5600:
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return 4;
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case PROCESSOR_XLP:
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@ -13343,6 +13382,9 @@ mips_multipass_dfa_lookahead (void)
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if (TUNE_OCTEON)
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return 2;
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if (TUNE_P5600)
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return 4;
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return 0;
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}
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@ -264,6 +264,7 @@ struct mips_cpu_info {
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|| mips_tune == PROCESSOR_OCTEON2)
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#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
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|| mips_tune == PROCESSOR_SB1A)
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#define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
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/* Whether vector modes and intrinsics for ST Microelectronics
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Loongson-2E/2F processors should be enabled. In o32 pairs of
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@ -306,7 +307,8 @@ struct mips_cpu_info {
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#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
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|| TUNE_MIPS4120 \
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|| TUNE_MIPS4130 \
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|| TUNE_24K)
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|| TUNE_24K \
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|| TUNE_P5600)
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#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
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#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
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@ -724,7 +726,7 @@ struct mips_cpu_info {
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%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
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|march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
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%{march=mips32r3: -mips32r3} \
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%{march=mips32r5: -mips32r5} \
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%{march=mips32r5|march=p5600: -mips32r5} \
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%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
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|march=xlr: -mips64} \
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%{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
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@ -65,6 +65,7 @@
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sr71000
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xlr
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xlp
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p5600
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])
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(define_c_enum "unspec" [
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@ -1050,6 +1051,7 @@
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(eq_attr "type" "ghost")
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"nothing")
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(include "p5600.md")
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(include "4k.md")
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(include "5k.md")
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(include "20kc.md")
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204
gcc/config/mips/p5600.md
Normal file
204
gcc/config/mips/p5600.md
Normal file
@ -0,0 +1,204 @@
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;; DFA-based pipeline description for P5600.
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;;
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;; Copyright (C) 2007-2014 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "p5600_agen_pipe, p5600_alu_pipe, p5600_fpu_pipe")
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;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes
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(define_cpu_unit "p5600_agq, p5600_al2, p5600_ctistd, p5600_ldsta,
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p5600_gpdiv" "p5600_agen_pipe")
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;; The arithmetic-logic-unit queue (ALQ) has ALU pipe
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(define_cpu_unit "p5600_alq, p5600_alu" "p5600_alu_pipe")
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;; The floating-point-unit queue (FPQ) has short and long pipes
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(define_cpu_unit "p5600_fpu_short, p5600_fpu_long" "p5600_fpu_pipe")
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;; Short FPU pipeline
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(define_cpu_unit "p5600_fpu_store" "p5600_fpu_pipe")
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;; Long FPU pipeline
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(define_cpu_unit "p5600_fpu_apu" "p5600_fpu_pipe")
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(define_reservation "p5600_agq_al2" "p5600_agq, p5600_al2")
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(define_reservation "p5600_agq_ctistd" "p5600_agq, p5600_ctistd")
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(define_reservation "p5600_agq_ldsta" "p5600_agq, p5600_ldsta")
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(define_reservation "p5600_alq_alu" "p5600_alq, p5600_alu")
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;;
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;; FPU pipe
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;;
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;; fadd, fsub
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(define_insn_reservation "p5600_fpu_fadd" 4
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(eq_attr "type" "fadd,fabs,fneg")
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"p5600_fpu_long, p5600_fpu_apu")
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;; fabs, fneg, fcmp
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(define_insn_reservation "p5600_fpu_fabs" 2
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(eq_attr "type" "fabs,fneg,fcmp,fmove")
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"p5600_fpu_short, p5600_fpu_apu")
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;; fload
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(define_insn_reservation "p5600_fpu_fload" 8
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(eq_attr "type" "fpload,fpidxload")
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"p5600_fpu_long, p5600_fpu_apu")
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;; fstore
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(define_insn_reservation "p5600_fpu_fstore" 1
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(eq_attr "type" "fpstore,fpidxstore")
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"p5600_fpu_short, p5600_fpu_apu")
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;; fmadd
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(define_insn_reservation "p5600_fpu_fmadd" 9
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(eq_attr "type" "fmadd")
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"p5600_fpu_long, p5600_fpu_apu")
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;; fmul
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(define_insn_reservation "p5600_fpu_fmul" 5
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(eq_attr "type" "fmul")
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"p5600_fpu_long, p5600_fpu_apu")
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;; fdiv, fsqrt
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(define_insn_reservation "p5600_fpu_div" 17
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(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
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"p5600_fpu_long, p5600_fpu_apu*17")
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;; fcvt
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(define_insn_reservation "p5600_fpu_fcvt" 4
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(eq_attr "type" "fcvt")
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"p5600_fpu_long, p5600_fpu_apu")
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;; mtc
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(define_insn_reservation "p5600_fpu_fmtc" 7
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(eq_attr "type" "mtc")
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"p5600_fpu_short, p5600_fpu_store")
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;; mfc
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(define_insn_reservation "p5600_fpu_fmfc" 4
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(eq_attr "type" "mfc")
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"p5600_fpu_short, p5600_fpu_store")
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;; madd/msub feeding into the add source
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;; madd.fmt dst, x, y, z -> madd.fmt a, dst, b, c 5 cycles
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(define_bypass 5 "p5600_fpu_fmadd" "p5600_fpu_fmadd" "mips_fmadd_bypass")
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;;
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;; Integer pipe
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;;
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;; and
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(define_insn_reservation "p5600_int_and" 1
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(eq_attr "move_type" "logical")
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"p5600_alq_alu")
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;; lui
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(define_insn_reservation "p5600_int_lui" 1
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(eq_attr "move_type" "const")
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"p5600_alq_alu")
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;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
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(define_insn_reservation "p5600_int_load" 4
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(eq_attr "move_type" "load")
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"p5600_agq_ldsta")
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;; store
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(define_insn_reservation "p5600_int_store" 3
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(eq_attr "move_type" "store")
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"p5600_agq_ldsta")
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;; andi, sll, srl, seb, seh
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(define_insn_reservation "p5600_int_arith_1" 1
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(eq_attr "move_type" "andi,sll0,signext")
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"p5600_agq_al2 | p5600_alq_alu")
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;; addi, addiu, ori, xori, add, addu
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(define_insn_reservation "p5600_int_arith_2" 1
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||||
(eq_attr "alu_type" "add,or,xor")
|
||||
"p5600_agq_al2 | p5600_alq_alu")
|
||||
|
||||
;; nor, sub
|
||||
(define_insn_reservation "p5600_int_arith_3" 1
|
||||
(eq_attr "alu_type" "nor,sub")
|
||||
"p5600_alq_alu")
|
||||
|
||||
;; srl, sra, rotr, slt, sllv, srlv
|
||||
(define_insn_reservation "p5600_int_arith_4" 1
|
||||
(eq_attr "type" "shift,slt,move")
|
||||
"p5600_agq_al2 | p5600_alq_alu")
|
||||
|
||||
;; nop
|
||||
(define_insn_reservation "p5600_int_nop" 0
|
||||
(eq_attr "type" "nop")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; clo, clz
|
||||
(define_insn_reservation "p5600_int_countbits" 1
|
||||
(eq_attr "type" "clz")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; Conditional moves
|
||||
(define_insn_reservation "p5600_int_condmove" 1
|
||||
(eq_attr "type" "condmove")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; madd, msub
|
||||
(define_insn_reservation "p5600_dsp_mac" 5
|
||||
(eq_attr "type" "imadd")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; mfhi/lo
|
||||
(define_insn_reservation "p5600_dsp_mfhilo" 1
|
||||
(eq_attr "type" "mfhi,mflo")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; mthi/lo
|
||||
(define_insn_reservation "p5600_dsp_mthilo" 5
|
||||
(eq_attr "type" "mthi,mtlo")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; mult, multu, mul
|
||||
(define_insn_reservation "p5600_dsp_mult" 5
|
||||
(eq_attr "type" "imul3,imul")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; branch and jump
|
||||
(define_insn_reservation "p5600_int_branch" 1
|
||||
(eq_attr "type" "branch,jump")
|
||||
"p5600_agq_ctistd")
|
||||
|
||||
;; prefetch
|
||||
(define_insn_reservation "p5600_int_prefetch" 3
|
||||
(eq_attr "type" "prefetch,prefetchx")
|
||||
"p5600_agq_ldsta")
|
||||
|
||||
;; divide
|
||||
(define_insn_reservation "p5600_int_div" 8
|
||||
(eq_attr "type" "idiv")
|
||||
"p5600_agq_al2+p5600_gpdiv*8")
|
||||
|
||||
;; arith
|
||||
(define_insn_reservation "p5600_int_arith_5" 2
|
||||
(eq_attr "type" "arith")
|
||||
"p5600_agq_al2")
|
||||
|
||||
;; call
|
||||
(define_insn_reservation "p5600_int_call" 2
|
||||
(eq_attr "jal" "indirect,direct")
|
||||
"p5600_agq_ctistd")
|
||||
@ -17209,6 +17209,7 @@ The processor names are:
|
||||
@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
|
||||
@samp{octeon}, @samp{octeon+}, @samp{octeon2},
|
||||
@samp{orion},
|
||||
@samp{p5600},
|
||||
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
|
||||
@samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000},
|
||||
@samp{rm7000}, @samp{rm9000},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user