i386.c (standard_sse_constant_p): Simplify switch statement.
* config/i386/i386.c (standard_sse_constant_p) <case 1>: Simplify switch statement. * config/i386/i386.md (*movdf_internal_rex64) <case 8,9,10>: Ditto. (*movdf_internal) <case 6,7,8>: Ditto. * config/i386/constraints.md (Y4): New constraint. * config/i386/sse.md (vec_set<mode>_0): Merge with *vec_set<mode>_0_sse4_1 and *vec_set<mode>_0_sse2. (*vec_extractv2di_1): Merge from *vec_extractv2di_1_sse2 and *vec_extractv2di_1_sse. (*vec_concatv2di_rex64): Merge from *vec_concatv2di_rex64_sse4_1 and *vec_concatv2di_rex64_sse. testsuite/ChangeLog: * gcc.target/i386/sse2-init-v2di-2: Update scan-assembler-times string. From-SVN: r174570
This commit is contained in:
Uros Bizjak
parent
162b5a21ad
commit
aad617322c
@ -1,3 +1,18 @@
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2011-06-02 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c (standard_sse_constant_p) <case 1>:
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Simplify switch statement.
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* config/i386/i386.md (*movdf_internal_rex64) <case 8,9,10>: Ditto.
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(*movdf_internal) <case 6,7,8>: Ditto.
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* config/i386/constraints.md (Y4): New constraint.
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* config/i386/sse.md (vec_set<mode>_0): Merge with
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*vec_set<mode>_0_sse4_1 and *vec_set<mode>_0_sse2.
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(*vec_extractv2di_1): Merge from *vec_extractv2di_1_sse2 and
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*vec_extractv2di_1_sse.
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(*vec_concatv2di_rex64): Merge from *vec_concatv2di_rex64_sse4_1
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and *vec_concatv2di_rex64_sse.
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2011-06-02 Stuart Henderson <shenders@gcc.gnu.org>
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PR target/48807
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@ -134,20 +149,17 @@
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(sigill_hdlr): New function.
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(set_fast_math) [!__x86_64__ && __sun__ && __svr4__]: Check if SSE
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insns can be executed.
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* config/sol2.h (ENDFILE_SPEC): Use crtfastmath.o if -ffast-math
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etc.
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* config/sol2.h (ENDFILE_SPEC): Use crtfastmath.o if -ffast-math etc.
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* config/sparc/sol2.h (ENDFILE_SPEC): Remove.
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2011-06-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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* config/t-slibgcc-darwin: Move to ...
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* config/t-slibgcc-dummy: .. this.
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Clarify comments.
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* config/t-slibgcc-dummy: ... this. Clarify comments.
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* config.gcc (i[34567]86-*-darwin*, x86_64-*-darwin*,
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powerpc-*-darwin*, powerpc64-*-darwin*): Reflect this.
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(i[3456x]86-*-netware*): Add t-slibgcc-dummy to tmake_file.
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(i[34567]86-*-rtems*): Remove extra_parts.
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Use i386/t-rtems.
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(i[34567]86-*-rtems*): Remove extra_parts. Use i386/t-rtems.
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Remove i386/t-crtstuff from tmake_file.
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(i[34567]86-*-solaris2*): Remove t-svr4,
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t-slibgcc-elf-ver, t-slibgcc-sld from tmake_file, add
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@ -417,8 +429,7 @@
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2011-05-30 H.J. Lu <hongjiu.lu@intel.com>
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PR target/49168
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* config/i386/i386.md (*movtf_internal): Handle misaligned
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load/store.
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* config/i386/i386.md (*movtf_internal): Handle misaligned load/store.
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2011-05-30 Jakub Jelinek <jakub@redhat.com>
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@ -99,6 +99,9 @@
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(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE2 is enabled.")
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(define_register_constraint "Y4" "TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE4_1 is enabled.")
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(define_register_constraint "Yi"
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"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
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@ -8601,33 +8601,28 @@ standard_sse_constant_opcode (rtx insn, rtx x)
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case 1:
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switch (get_attr_mode (insn))
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{
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case MODE_TI:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vpxor\t%0, %d0";
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case MODE_V2DF:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vxorpd\t%0, %d0";
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case MODE_V4SF:
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return "%vxorps\t%0, %d0";
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case MODE_V2DF:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vxorps\t%0, %d0";
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else
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return "%vxorpd\t%0, %d0";
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case MODE_TI:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vxorps\t%0, %d0";
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else
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return "%vpxor\t%0, %d0";
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case MODE_OI:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "vpxor\t%x0, %x0, %x0";
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case MODE_V4DF:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "vxorpd\t%x0, %x0, %x0";
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case MODE_V8SF:
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return "vxorps\t%x0, %x0, %x0";
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case MODE_V4DF:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "vxorps\t%x0, %x0, %x0";
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else
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return "vxorpd\t%x0, %x0, %x0";
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case MODE_OI:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "vxorps\t%x0, %x0, %x0";
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else
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return "vpxor\t%x0, %x0, %x0";
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default:
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break;
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}
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case 2:
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return "%vpcmpeqd\t%0, %d0";
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default:
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@ -2956,18 +2956,15 @@
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case 10:
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switch (get_attr_mode (insn))
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{
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case MODE_TI:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V2DF:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovapd\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_V2DF:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovapd\t{%1, %0|%0, %1}";
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case MODE_TI:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_DI:
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return "%vmovq\t{%1, %0|%0, %1}";
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case MODE_DF:
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@ -3102,18 +3099,15 @@
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case 8:
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switch (get_attr_mode (insn))
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{
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case MODE_TI:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V2DF:
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if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovapd\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_V2DF:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovapd\t{%1, %0|%0, %1}";
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case MODE_TI:
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if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_DI:
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return "%vmovq\t{%1, %0|%0, %1}";
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case MODE_DF:
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@ -3376,79 +3376,35 @@
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;; Avoid combining registers from different units in a single alternative,
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;; see comment above inline_secondary_memory_needed function in i386.c
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(define_insn "*vec_set<mode>_0_sse4_1"
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(define_insn "vec_set<mode>_0"
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[(set (match_operand:VI4F_128 0 "nonimmediate_operand"
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"=x,x,x ,x,x,x ,x ,m,m,m")
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"=Y4,Y2,Y2,x,x,x,Y4 ,x ,m,m,m")
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(vec_merge:VI4F_128
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(vec_duplicate:VI4F_128
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(match_operand:<ssescalarmode> 2 "general_operand"
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" x,m,*r,x,x,*rm,*rm,x,*r,fF"))
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" Y4,m ,*r,m,x,x,*rm,*rm,x,*r,fF"))
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(match_operand:VI4F_128 1 "vector_move_operand"
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" C,C,C ,0,x,0 ,x ,0,0 ,0")
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" C ,C ,C ,C,0,x,0 ,x ,0,0 ,0")
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(const_int 1)))]
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"TARGET_SSE4_1"
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"TARGET_SSE"
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"@
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%vinsertps\t{$0xe, %d2, %0|%0, %d2, 0xe}
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%vmov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
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%vmovd\t{%2, %0|%0, %2}
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movss\t{%2, %0|%0, %2}
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movss\t{%2, %0|%0, %2}
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vmovss\t{%2, %1, %0|%0, %1, %2}
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pinsrd\t{$0, %2, %0|%0, %2, 0}
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vpinsrd\t{$0, %2, %1, %0|%0, %1, %2, 0}
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#
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#
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#"
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[(set_attr "isa" "base,base,base,noavx,avx,noavx,avx,base,base,base")
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(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov,sselog,sselog,*,*,*")
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(set_attr "prefix_extra" "*,*,*,*,*,1,1,*,*,*")
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(set_attr "length_immediate" "*,*,*,*,*,1,1,*,*,*")
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(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,orig,vex,orig,vex,*,*,*")
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(set_attr "mode" "SF,<ssescalarmode>,SI,SF,SF,TI,TI,*,*,*")])
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;; Avoid combining registers from different units in a single alternative,
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;; see comment above inline_secondary_memory_needed function in i386.c
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(define_insn "*vec_set<mode>_0_sse2"
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[(set (match_operand:VI4F_128 0 "nonimmediate_operand"
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"=x,x ,x,m,m ,m")
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(vec_merge:VI4F_128
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(vec_duplicate:VI4F_128
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(match_operand:<ssescalarmode> 2 "general_operand"
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" m,*r,x,x,*r,fF"))
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(match_operand:VI4F_128 1 "vector_move_operand"
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" C, C,0,0,0 ,0")
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(const_int 1)))]
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"TARGET_SSE2"
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"@
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mov<ssescalarmodesuffix>\t{%2, %0|%0, %2}
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movd\t{%2, %0|%0, %2}
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movss\t{%2, %0|%0, %2}
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#
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#
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#"
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[(set_attr "type" "ssemov")
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(set_attr "mode" "<ssescalarmode>,SI,SF,*,*,*")])
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;; Avoid combining registers from different units in a single alternative,
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;; see comment above inline_secondary_memory_needed function in i386.c
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(define_insn "vec_set<mode>_0"
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[(set (match_operand:VI4F_128 0 "nonimmediate_operand"
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"=x,x,m,m ,m")
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(vec_merge:VI4F_128
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(vec_duplicate:VI4F_128
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(match_operand:<ssescalarmode> 2 "general_operand"
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" m,x,x,*r,fF"))
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(match_operand:VI4F_128 1 "vector_move_operand"
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" C,0,0,0 ,0")
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(const_int 1)))]
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"TARGET_SSE"
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"@
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movss\t{%2, %0|%0, %2}
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movss\t{%2, %0|%0, %2}
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#
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#
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#"
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[(set_attr "type" "ssemov")
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(set_attr "mode" "SF,SF,*,*,*")])
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[(set_attr "isa" "base,base,base,noavx,noavx,avx,noavx,avx,base,base,base")
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(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov,ssemov,sselog,sselog,*,*,*")
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(set_attr "prefix_extra" "*,*,*,*,*,*,1,1,*,*,*")
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(set_attr "length_immediate" "*,*,*,*,*,*,1,1,*,*,*")
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(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,orig,orig,vex,orig,vex,*,*,*")
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(set_attr "mode" "SF,<ssescalarmode>,SI,SF,SF,SF,TI,TI,*,*,*")])
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;; A subset is vec_setv4sf.
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(define_insn "*vec_setv4sf_sse4_1"
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@ -6214,7 +6170,7 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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;; It must come before *vec_extractv2di_1_sse since it is preferred.
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;; It must come before *vec_extractv2di_1_rex64 since it is preferred.
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(define_insn "*sse4_1_pextrq"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(vec_select:DI
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@ -6478,39 +6434,26 @@
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(set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig")
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(set_attr "mode" "V2SF,TI,TI,TI,DI")])
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(define_insn "*vec_extractv2di_1_sse2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x")
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(define_insn "*vec_extractv2di_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=m,Y2,Y2,Y2,x,x")
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(vec_select:DI
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(match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o")
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(match_operand:V2DI 1 "nonimmediate_operand" " x,0 ,Y2,o ,x,o")
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(parallel [(const_int 1)])))]
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"!TARGET_64BIT
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&& TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"!TARGET_64BIT && TARGET_SSE
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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%vmovhps\t{%1, %0|%0, %1}
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psrldq\t{$8, %0|%0, 8}
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vpsrldq\t{$8, %1, %0|%0, %1, 8}
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%vmovq\t{%H1, %0|%0, %H1}"
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[(set_attr "isa" "base,noavx,avx,base")
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(set_attr "type" "ssemov,sseishft1,sseishft1,ssemov")
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(set_attr "length_immediate" "*,1,1,*")
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(set_attr "memory" "*,none,none,*")
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(set_attr "prefix" "maybe_vex,orig,vex,maybe_vex")
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(set_attr "mode" "V2SF,TI,TI,TI")])
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;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
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(define_insn "*vec_extractv2di_1_sse"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
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(vec_select:DI
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(match_operand:V2DI 1 "nonimmediate_operand" " x,x,o")
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(parallel [(const_int 1)])))]
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"!TARGET_SSE2 && TARGET_SSE
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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movhps\t{%1, %0|%0, %1}
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%vmovq\t{%H1, %0|%0, %H1}
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movhlps\t{%1, %0|%0, %1}
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movlps\t{%H1, %0|%0, %H1}"
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[(set_attr "type" "ssemov")
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(set_attr "mode" "V2SF,V4SF,V2SF")])
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[(set_attr "isa" "base,noavx,avx,base,noavx,noavx")
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(set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov")
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(set_attr "length_immediate" "*,1,1,*,*,*")
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(set_attr "memory" "*,none,none,*,*,*")
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(set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig")
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(set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF")])
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(define_insn "*vec_dupv4si_avx"
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[(set (match_operand:V4SI 0 "register_operand" "=x,x")
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@ -6570,8 +6513,8 @@
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(match_operand:SI 2 "vector_move_operand" "rm,rm,x,x, C,*ym, C")))]
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"TARGET_SSE4_1"
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"@
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pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
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vpinsrd\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
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pinsrd\t{$1, %2, %0|%0, %2, 1}
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vpinsrd\t{$1, %2, %1, %0|%0, %1, %2, 1}
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punpckldq\t{%2, %0|%0, %2}
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vpunpckldq\t{%2, %1, %0|%0, %1, %2}
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%vmovd\t{%1, %0|%0, %1}
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@ -6633,18 +6576,18 @@
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(set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")])
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;; movd instead of movq is required to handle broken assemblers.
|
||||
(define_insn "*vec_concatv2di_rex64_sse4_1"
|
||||
(define_insn "*vec_concatv2di_rex64"
|
||||
[(set (match_operand:V2DI 0 "register_operand"
|
||||
"=x, x, x,Yi,!x,x,x,x,x")
|
||||
"=Y4,x ,x ,Yi,!x,x,x,x,x")
|
||||
(vec_concat:V2DI
|
||||
(match_operand:DI 1 "nonimmediate_operand"
|
||||
" 0, x,xm,r ,*y,0,x,0,x")
|
||||
" 0 ,x ,xm,r ,*y,0,x,0,x")
|
||||
(match_operand:DI 2 "vector_move_operand"
|
||||
"rm,rm, C,C ,C ,x,x,m,m")))]
|
||||
"TARGET_64BIT && TARGET_SSE4_1"
|
||||
" rm,rm,C ,C ,C ,x,x,m,m")))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
|
||||
vpinsrq\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
|
||||
pinsrq\t{$1, %2, %0|%0, %2, 1}
|
||||
vpinsrq\t{$1, %2, %1, %0|%0, %1, %2, 1}
|
||||
%vmovq\t{%1, %0|%0, %1}
|
||||
%vmovd\t{%1, %0|%0, %1}
|
||||
movq2dq\t{%1, %0|%0, %1}
|
||||
@ -6653,7 +6596,11 @@
|
||||
movhps\t{%2, %0|%0, %2}
|
||||
vmovhps\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx,base,base,base,noavx,avx,noavx,avx")
|
||||
(set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov,sselog,sselog,ssemov,ssemov")
|
||||
(set (attr "type")
|
||||
(if_then_else
|
||||
(eq_attr "alternative" "0,1,5,6")
|
||||
(const_string "sselog")
|
||||
(const_string "ssemov")))
|
||||
(set (attr "prefix_rex")
|
||||
(if_then_else
|
||||
(and (eq_attr "alternative" "0,3")
|
||||
@ -6665,24 +6612,6 @@
|
||||
(set_attr "prefix" "orig,vex,maybe_vex,maybe_vex,orig,orig,vex,orig,vex")
|
||||
(set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,V2SF,V2SF")])
|
||||
|
||||
;; movd instead of movq is required to handle broken assemblers.
|
||||
(define_insn "*vec_concatv2di_rex64_sse"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=Y2,Yi,!Y2,Y2,x,x")
|
||||
(vec_concat:V2DI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "Y2m,r ,*y ,0 ,0,0")
|
||||
(match_operand:DI 2 "vector_move_operand" " C ,C ,C ,Y2,x,m")))]
|
||||
"TARGET_64BIT && TARGET_SSE"
|
||||
"@
|
||||
movq\t{%1, %0|%0, %1}
|
||||
movd\t{%1, %0|%0, %1}
|
||||
movq2dq\t{%1, %0|%0, %1}
|
||||
punpcklqdq\t{%2, %0|%0, %2}
|
||||
movlhps\t{%2, %0|%0, %2}
|
||||
movhps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
|
||||
(set_attr "prefix_rex" "*,1,*,*,*,*")
|
||||
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
|
||||
|
||||
(define_insn "vec_concatv2di"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x,x")
|
||||
(vec_concat:V2DI
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
2011-06-02 Uros Bizjak <ubizjak@gmail.com>
|
||||
|
||||
* gcc.target/i386/sse2-init-v2di-2: Update scan-assembler-times string.
|
||||
|
||||
2011-06-02 Steven G. Kargl <kargl@gcc.gnu.org>
|
||||
|
||||
PR fortran/49265
|
||||
|
||||
@ -10,4 +10,4 @@ test (long long b)
|
||||
return _mm_cvtsi64_si128 (b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64_sse4_1/4" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64/4" 1 } } */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user