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[AArch64] Fix PR/65770 vstN_lane on bigendian

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gcc/:

	* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>,
	vec_store_lanesci_lane<mode>, vec_store_lanesxi_lane<mode>):
	Flip lane index back at assembly time for bigendian.

gcc/testsuite/:

	* gcc.target/aarch64/vstN_lane_1.c: New file.

From-SVN: r222582
This commit is contained in:
Alan Lawrence 2015-04-29 16:10:27 +00:00 committed by Alan Lawrence
parent 952bc7a64c
commit aaf3de7ab2
4 changed files with 102 additions and 3 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2015-04-29 Alan Lawrence <alan.lawrence@arm.com>
PR target/65770
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>,
vec_store_lanesci_lane<mode>, vec_store_lanesxi_lane<mode>):
Flip lane index back at assembly time for bigendian.
2015-04-29 Thomas Schwinge <thomas@codesourcery.com>
* tree.h (OMP_STANDALONE_CLAUSES): New macro.

18
gcc/config/aarch64/aarch64-simd.md
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@ -3954,6 +3954,7 @@
[(set_attr "type" "neon_store2_2reg<q>")]
)
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn "vec_store_lanesoi_lane<mode>"
[(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
@ -3961,7 +3962,10 @@
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST2_LANE))]
"TARGET_SIMD"
"st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
return "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0";
}
[(set_attr "type" "neon_store3_one_lane<q>")]
)
@ -4045,6 +4049,7 @@
[(set_attr "type" "neon_store3_3reg<q>")]
)
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn "vec_store_lanesci_lane<mode>"
[(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
@ -4052,7 +4057,10 @@
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST3_LANE))]
"TARGET_SIMD"
"st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
return "st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0";
}
[(set_attr "type" "neon_store3_one_lane<q>")]
)
@ -4136,6 +4144,7 @@
[(set_attr "type" "neon_store4_4reg<q>")]
)
;; RTL uses GCC vector extension indices, so flip only for assembly.
(define_insn "vec_store_lanesxi_lane<mode>"
[(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
@ -4143,7 +4152,10 @@
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_ST4_LANE))]
"TARGET_SIMD"
"st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0"
{
operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
return "st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0";
}
[(set_attr "type" "neon_store4_one_lane<q>")]
)

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2015-04-29 Alan Lawrence <alan.lawrence@arm.com>
PR target/65770
* gcc.target/aarch64/vstN_lane_1.c: New file.
2015-04-29 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/64667

75
gcc/testsuite/gcc.target/aarch64/vstN_lane_1.c Normal file
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@ -0,0 +1,75 @@
/* { dg-do run } */
/* { dg-options "-O3 -fno-inline" } */
#include <arm_neon.h>
extern void abort (void);
#define VARIANTS(VARIANT, STRUCT) \
VARIANT (uint8, , 8, _u8, 6, STRUCT) \
VARIANT (uint16, , 4, _u16, 3, STRUCT) \
VARIANT (uint32, , 2, _u32, 1, STRUCT) \
VARIANT (uint64, , 1, _u64, 0, STRUCT) \
VARIANT (int8, , 8, _s8, 5, STRUCT) \
VARIANT (int16, , 4, _s16, 2, STRUCT) \
VARIANT (int32, , 2, _s32, 0, STRUCT) \
VARIANT (int64, , 1, _s64, 0, STRUCT) \
VARIANT (poly8, , 8, _p8, 7, STRUCT) \
VARIANT (poly16, , 4, _p16, 1, STRUCT) \
VARIANT (float32, , 2, _f32, 1, STRUCT) \
VARIANT (float64, , 1, _f64, 0, STRUCT) \
VARIANT (uint8, q, 16, _u8, 14, STRUCT) \
VARIANT (uint16, q, 8, _u16, 4, STRUCT) \
VARIANT (uint32, q, 4, _u32, 3, STRUCT) \
VARIANT (uint64, q, 2, _u64, 0, STRUCT) \
VARIANT (int8, q, 16, _s8, 13, STRUCT) \
VARIANT (int16, q, 8, _s16, 6, STRUCT) \
VARIANT (int32, q, 4, _s32, 2, STRUCT) \
VARIANT (int64, q, 2, _s64, 1, STRUCT) \
VARIANT (poly8, q, 16, _p8, 12, STRUCT) \
VARIANT (poly16, q, 8, _p16, 5, STRUCT) \
VARIANT (float32, q, 4, _f32, 1, STRUCT)\
VARIANT (float64, q, 2, _f64, 0, STRUCT)
#define TESTMETH(BASE, Q, ELTS, SUFFIX, LANE, STRUCT) \
int \
test_vst##STRUCT##Q##_lane##SUFFIX (const BASE##_t *data) \
{ \
BASE##x##ELTS##x##STRUCT##_t vectors; \
for (int i = 0; i < STRUCT; i++, data += ELTS) \
vectors.val[i] = vld1##Q##SUFFIX (data); \
BASE##_t temp[STRUCT]; \
vst##STRUCT##Q##_lane##SUFFIX (temp, vectors, LANE); \
for (int i = 0; i < STRUCT; i++) \
{ \
if (temp[i] != vget##Q##_lane##SUFFIX (vectors.val[i], LANE)) \
return 1; \
} \
return 0; \
}
/* Tests of vst2_lane and vst2q_lane. */
VARIANTS (TESTMETH, 2)
/* Tests of vst3_lane and vst3q_lane. */
VARIANTS (TESTMETH, 3)
/* Tests of vst4_lane and vst4q_lane. */
VARIANTS (TESTMETH, 4)
#define CHECK(BASE, Q, ELTS, SUFFIX, LANE, STRUCT) \
if (test_vst##STRUCT##Q##_lane##SUFFIX ((const BASE##_t *)orig_data)) \
abort ();
int
main (int argc, char **argv)
{
/* Original data for all vector formats. */
uint64_t orig_data[8] = {0x1234567890abcdefULL, 0x13579bdf02468aceULL,
0x012389ab4567cdefULL, 0xfeeddadacafe0431ULL,
0x1032547698badcfeULL, 0xbadbadbadbad0badULL,
0x0102030405060708ULL, 0x0f0e0d0c0b0a0908ULL};
VARIANTS (CHECK, 2);
VARIANTS (CHECK, 3);
VARIANTS (CHECK, 4);
return 0;
}