From aafc814c7bbf7c176d50a99a3bbf898bc1c2c5dd Mon Sep 17 00:00:00 2001 From: Dwarakanath Rajagopal Date: Wed, 28 Mar 2007 21:44:56 +0000 Subject: [PATCH] Adding barcelona as a variant of amdfam10 architecture From-SVN: r123313 --- gcc/ChangeLog | 6 ++++++ gcc/config.gcc | 14 +++++++------- gcc/config/i386/i386.c | 4 ++++ gcc/doc/invoke.texi | 2 +- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5267e52b734..1df143557aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2007-03-28 Dwarakanath Rajagopal + + * config.gcc: Accept barcelona as a variant of amdfam10. + * config/i386/i386.c (override_options): Likewise. + * doc/invoke.texi: Likewise. + 2007-03-28 Eric Botcazou * tree-dfa.c (get_ref_base_and_extent): Do not expect positive diff --git a/gcc/config.gcc b/gcc/config.gcc index cc3f18e81eb..d1deffc92a4 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1129,14 +1129,14 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu) # FIXME: -m64 for i[34567]86-*-* should be allowed just # like -m32 for x86_64-*-*. case X"${with_cpu}" in - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xk8|Xopteron|Xathlon64|Xathlon-fx) + Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) ;; X) with_cpu=generic ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic core2 nocona x86-64 amdfam10 k8 opteron athlon64 athlon-fx" 1>&2 + echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 exit 1 ;; esac @@ -1258,14 +1258,14 @@ i[34567]86-*-solaris2*) # FIXME: -m64 for i[34567]86-*-* should be allowed just # like -m32 for x86_64-*-*. case X"${with_cpu}" in - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xk8|Xopteron|Xathlon64|Xathlon-fx) + Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) ;; X) with_cpu=generic ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic core2 nocona x86-64 amdfam10 k8 opteron athlon64 athlon-fx" 1>&2 + echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 exit 1 ;; esac @@ -2595,7 +2595,7 @@ if test x$with_cpu = x ; then ;; i686-*-* | i786-*-*) case ${target_noncanonical} in - amdfam10-*) + amdfam10-*|barcelona-*) with_cpu=amdfam10 ;; k8-*|opteron-*|athlon_64-*) @@ -2641,7 +2641,7 @@ if test x$with_cpu = x ; then ;; x86_64-*-*) case ${target_noncanonical} in - amdfam10-*) + amdfam10-*|barcelona-*) with_cpu=amdfam10 ;; k8-*|opteron-*|athlon_64-*) @@ -2923,7 +2923,7 @@ case "${target}" in esac # OK ;; - "" | amdfam10 | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) + "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) # OK ;; *) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 45876bde2ae..40ffcc87507 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1724,6 +1724,10 @@ override_options (void) | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT | PTA_ABM | PTA_SSE4A | PTA_CX16}, + {"barcelona", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW + | PTA_64BIT | PTA_3DNOW_A | PTA_SSE + | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT + | PTA_ABM | PTA_SSE4A | PTA_CX16}, {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ }, {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ }, }; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f2451c3812f..38552b7fd7b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9765,7 +9765,7 @@ instruction set support. @item k8, opteron, athlon64, athlon-fx AMD K8 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.) -@item amdfam10 +@item amdfam10, barcelona AMD Family 10 core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit instruction set extensions.)