sh.h (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New hook.
* config/sh/sh.h (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New hook. * config/sh/sync.md (atomic_test_and_set): New expander. (tasb, atomic_test_and_set_soft): New insns. * config/sh/sh.opt (menable-tas): New option. * doc/invoke.texi (SH Options): Document it. From-SVN: r184947
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@ -1,3 +1,11 @@
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2012-03-05 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/sh.h (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL): New hook.
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* config/sh/sync.md (atomic_test_and_set): New expander.
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(tasb, atomic_test_and_set_soft): New insns.
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* config/sh/sh.opt (menable-tas): New option.
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* doc/invoke.texi (SH Options): Document it.
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2012-03-05 Richard Guenther <rguenther@suse.de>
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* cfgloop.c (verify_loop_structure): Verify dominators before
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@ -2473,4 +2473,10 @@ extern int current_function_interrupt;
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/* FIXME: middle-end support for highpart optimizations is missing. */
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#define high_life_started reload_in_progress
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/* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80.
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This value is used by optabs.c atomic op expansion code as well as in
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sync.md. */
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#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
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#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
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#endif /* ! GCC_SH_H */
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@ -323,6 +323,10 @@ msoft-atomic
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Target Report Mask(SOFT_ATOMIC)
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Use software atomic sequences supported by kernel
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menable-tas
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Target Report RejectNegative Var(TARGET_ENABLE_TAS)
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Use tas.b instruction for __atomic_test_and_set
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mspace
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Target RejectNegative Alias(Os)
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Deprecated. Use -Os instead
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@ -404,3 +404,61 @@
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"1: mov r1,r15";
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}
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[(set_attr "length" "18")])
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(define_expand "atomic_test_and_set"
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[(match_operand:SI 0 "register_operand" "") ;; bool result output
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(match_operand:QI 1 "memory_operand" "") ;; memory
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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"(TARGET_SOFT_ATOMIC || TARGET_ENABLE_TAS) && !TARGET_SHMEDIA"
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{
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rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
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if (TARGET_ENABLE_TAS)
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emit_insn (gen_tasb (addr));
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else
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{
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rtx val = force_reg (QImode,
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gen_int_mode (TARGET_ATOMIC_TEST_AND_SET_TRUEVAL,
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QImode));
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emit_insn (gen_atomic_test_and_set_soft (addr, val));
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}
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/* The result of the test op is the inverse of what we are
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supposed to return. Thus invert the T bit. The inversion will be
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potentially optimized away and integrated into surrounding code. */
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emit_insn (gen_movnegt (operands[0]));
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DONE;
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})
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(define_insn "tasb"
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[(set (reg:SI T_REG)
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(eq:SI (mem:QI (match_operand:SI 0 "register_operand" "r"))
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(const_int 0)))
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(set (mem:QI (match_dup 0))
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(unspec:QI [(const_int 128)] UNSPEC_ATOMIC))]
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"TARGET_ENABLE_TAS && !TARGET_SHMEDIA"
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"tas.b @%0"
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[(set_attr "insn_class" "co_group")])
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(define_insn "atomic_test_and_set_soft"
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[(set (reg:SI T_REG)
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(eq:SI (mem:QI (match_operand:SI 0 "register_operand" "u"))
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(const_int 0)))
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(set (mem:QI (match_dup 0))
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(unspec:QI [(match_operand:QI 1 "register_operand" "u")] UNSPEC_ATOMIC))
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(clobber (match_scratch:QI 2 "=&u"))
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(clobber (reg:SI R0_REG))
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(clobber (reg:SI R1_REG))]
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"TARGET_SOFT_ATOMIC && !TARGET_ENABLE_TAS && !TARGET_SHMEDIA"
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{
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return "mova 1f,r0" "\n"
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" .align 2" "\n"
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" mov r15,r1" "\n"
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" mov #(0f-1f),r15" "\n"
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"0: mov.b @%0,%2" "\n"
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" mov.b %1,@%0" "\n"
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"1: mov r1,r15" "\n"
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" tst %2,%2";
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}
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[(set_attr "length" "16")])
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@ -887,7 +887,8 @@ See RS/6000 and PowerPC Options.
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-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
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-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
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-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol
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-mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mpretend-cmove}
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-mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mpretend-cmove @gol
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-menable-tas}
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@emph{Solaris 2 Options}
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@gccoptlist{-mimpure-text -mno-impure-text @gol
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@ -17934,6 +17935,15 @@ single-core systems. They will not perform correctly on multi-core systems.
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This option is enabled by default when the target is @code{sh-*-linux*}.
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For details on the atomic built-in functions see @ref{__atomic Builtins}.
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@item -menable-tas
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@opindex menable-tas
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Generate the @code{tas.b} opcode for @code{__atomic_test_and_set}.
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Notice that depending on the particular hardware and software configuration
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this can degrade overall performance due to the operand cache line flushes
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that are implied by the @code{tas.b} instruction. On multi-core SH4A
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processors the @code{tas.b} instruction must be used with caution since it
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can result in data corruption for certain cache configurations.
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@item -mspace
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@opindex mspace
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Optimize for space instead of speed. Implied by @option{-Os}.
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