MIPS: PR target/78176 add -mlxc1-sxc1.
gcc/ PR target/78176 * config.gcc (supported_defaults): Add lxc1-sxc1. (with_lxc1_sxc1): Add validation. (all_defaults): Add lxc1-sxc1. * config/mips/mips.opt (mlxc1-sxc1): New option. * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mlxc1-sxc1. (TARGET_CPU_CPP_BUILTINS): Add builtin_define for __mips_no_lxc1_sxc1. (ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1. * gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option. * doc/install.texi (--with-lxc1-sxc1): Document the new option. gcc/testsuite/ * gcc.target/mips/lxc1-sxc1-1.c: New file. * gcc.target/mips/lxc1-sxc1-2.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add ghost option HAS_LXC1. (mips_option_groups): Add -m[no-]lxc1-sxc1. (mips-dg-init): Detect default -mno-lxc1-sxc1. (mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade. From-SVN: r244640
This commit is contained in:
Matthew Fortune
parent
a08895999d
commit
ab6b44cb22
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@ -1,3 +1,18 @@
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2017-01-19 Doug Gilmore <doug.gilmore@imgtec.com>
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PR target/78176
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* config.gcc (supported_defaults): Add lxc1-sxc1.
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(with_lxc1_sxc1): Add validation.
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(all_defaults): Add lxc1-sxc1.
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* config/mips/mips.opt (mlxc1-sxc1): New option.
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* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
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mlxc1-sxc1.
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(TARGET_CPU_CPP_BUILTINS): Add builtin_define for
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__mips_no_lxc1_sxc1.
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(ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1.
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* gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option.
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* doc/install.texi (--with-lxc1-sxc1): Document the new option.
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2017-01-19 Richard Biener <rguenther@suse.de>
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PR tree-optimization/72488
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@ -3940,7 +3940,7 @@ case "${target}" in
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;;
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mips*-*-*)
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supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
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supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1"
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case ${with_float} in
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"" | soft | hard)
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@ -4063,6 +4063,21 @@ case "${target}" in
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exit 1
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;;
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esac
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case ${with_lxc1_sxc1} in
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yes)
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with_lxc1_sxc1=lxc1-sxc1
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;;
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no)
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with_lxc1_sxc1=no-lxc1-sxc1
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;;
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"")
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;;
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*)
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echo "Unknown lxc1-sxc1 type used in --with-lxc1-sxc1" 1>&2
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exit 1
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;;
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esac
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;;
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nds32*-*-*)
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@ -4496,7 +4511,7 @@ case ${target} in
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esac
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t=
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all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
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all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1"
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for option in $all_defaults
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do
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eval "val=\$with_"`echo $option | sed s/-/_/g`
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@ -637,6 +637,8 @@ struct mips_cpu_info {
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\
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if (TARGET_CACHE_BUILTIN) \
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builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
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if (!ISA_HAS_LXC1_SXC1) \
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builtin_define ("__mips_no_lxc1_sxc1"); \
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} \
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while (0)
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@ -866,7 +868,8 @@ struct mips_cpu_info {
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{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
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{"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
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{"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
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{"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
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{"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
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{"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" } \
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/* A spec that infers the:
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-mnan=2008 setting from a -mips argument,
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@ -1036,7 +1039,8 @@ struct mips_cpu_info {
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/* ISA has floating-point indexed load and store instructions
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(LWXC1, LDXC1, SWXC1 and SDXC1). */
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#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
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#define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
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&& mips_lxc1_sxc1)
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/* ISA has paired-single instructions. */
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#define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
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@ -388,6 +388,10 @@ mlra
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Target Report Var(mips_lra_flag) Init(1) Save
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Use LRA instead of reload.
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mlxc1-sxc1
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Target Report Var(mips_lxc1_sxc1) Init(1)
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Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
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mtune=
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Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
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-mtune=PROCESSOR Optimize the output for PROCESSOR.
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@ -1375,6 +1375,25 @@ On MIPS targets, make @option{-msynci} the default when no
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On MIPS targets, make @option{-mno-synci} the default when no
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@option{-msynci} option is passed. This is the default.
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@item --with-lxc1-sxc1
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On MIPS targets, make @option{-mlxc1-sxc1} the default when no
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@option{-mno-lxc1-sxc1} option is passed. This is the default.
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@item --without-lxc1-sxc1
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On MIPS targets, make @option{-mno-lxc1-sxc1} the default when no
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@option{-mlxc1-sxc1} option is passed. The indexed load/store
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instructions are not directly a problem but can lead to unexpected
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behaviour when deployed in an application intended for a 32-bit address
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space but run on a 64-bit processor. The issue is seen because all
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known MIPS 64-bit Linux kernels execute o32 and n32 applications
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with 64-bit addressing enabled which affects the overflow behaviour
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of the indexed addressing mode. GCC will assume that ordinary
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32-bit arithmetic overflow behaviour is the same whether performed
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as an @code{addu} instruction or as part of the address calculation
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in @code{lwxc1} type instructions. This assumption holds true in a
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pure 32-bit environment and can hold true in a 64-bit environment if
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the address space is accurately set to be 32-bit for o32 and n32.
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@item --with-mips-plt
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On MIPS targets, make use of copy relocations and PLTs.
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These features are extensions to the traditional
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@ -19932,6 +19932,12 @@ it is unused.
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This optimization is off by default at all optimization levels.
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@item -mlxc1-sxc1
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@itemx -mno-lxc1-sxc1
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@opindex mlxc1-sxc1
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When applicable, enable (disable) the generation of @code{lwxc1},
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@code{swxc1}, @code{ldxc1}, @code{sdxc1} instructions. Enabled by default.
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@end table
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@node MMIX Options
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@ -1,3 +1,14 @@
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2017-01-19 Matthew Fortune <matthew.fortune@imgtec.com>
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PR target/78176
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* gcc.target/mips/lxc1-sxc1-1.c: New file.
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* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
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* gcc.target/mips/mips.exp (mips_option_groups): Add ghost option
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HAS_LXC1.
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(mips_option_groups): Add -m[no-]lxc1-sxc1.
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(mips-dg-init): Detect default -mno-lxc1-sxc1.
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(mips-dg-options): Handle HAS_LXC1 arch upgrade/downgrade.
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2017-01-19 Andre Vehreschild <vehre@gcc.gnu.org>
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PR fortran/70696
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@ -0,0 +1,60 @@
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/* { dg-options "(HAS_LXC1) -mno-lxc1-sxc1" } */
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/* { dg-final { scan-assembler-not "\tldxc1\t" } } */
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/* { dg-final { scan-assembler-not "\tsdxc1\t" } } */
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#ifndef __mips_no_lxc1_sxc1
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#error missing definition of __mips_no_lxc1_sxc1
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#endif
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double ldexp(double x, int exp);
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typedef struct
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{
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double** rows;
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} d_mat_struct;
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typedef d_mat_struct d_mat_t[1];
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#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
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double __attribute__((noinline))
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ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
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{
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int kappa2 = kappa;
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double tmp = 0.0;
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do
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{
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kappa--;
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if (kappa > zeros + 1)
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{
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tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
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tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
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}
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}
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while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
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return tmp;
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}
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#define SIZE 20
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int main(void)
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{
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int kappa = SIZE - 1;
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int zeros = 1;
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double ctt = 2;
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int expo[SIZE] = {0};
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double s[SIZE] = {0};
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double rows_data[SIZE][SIZE] = {0};
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double* rows[SIZE];
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for (int i = 0; i < SIZE; i++)
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rows[i] = rows_data[i];
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d_mat_t r = { rows };
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ldxc1_test(kappa, zeros, ctt, expo, r, s);
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return 0;
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}
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@ -0,0 +1,60 @@
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/* { dg-options "(HAS_LXC1) -mlxc1-sxc1" } */
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/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
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/* { dg-final { scan-assembler "\tldxc1\t" } } */
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#ifdef __mips_no_lxc1_sxc1
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#error unexpected definition of __mips_no_lxc1_sxc1
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#endif
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double ldexp(double x, int exp);
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typedef struct
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{
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double** rows;
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} d_mat_struct;
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typedef d_mat_struct d_mat_t[1];
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#define d_mat_entry(mat,i,j) (*((mat)->rows[i] + (j)))
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double __attribute__((noinline))
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ldxc1_test (int kappa, int zeros, double ctt, int* expo, d_mat_t r, double* s)
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{
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int kappa2 = kappa;
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double tmp = 0.0;
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do
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{
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kappa--;
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if (kappa > zeros + 1)
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{
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tmp = d_mat_entry(r, kappa - 1, kappa - 1) * ctt;
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tmp = ldexp(tmp, (expo[kappa - 1] - expo[kappa2]));
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}
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}
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while ((kappa >= zeros + 2) && (s[kappa - 1] <= tmp));
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return tmp;
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}
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#define SIZE 20
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int main(void)
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{
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int kappa = SIZE - 1;
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int zeros = 1;
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double ctt = 2;
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int expo[SIZE] = {0};
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double s[SIZE] = {0};
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double rows_data[SIZE][SIZE] = {0};
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double* rows[SIZE];
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for (int i = 0; i < SIZE; i++)
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rows[i] = rows_data[i];
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d_mat_t r = { rows };
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ldxc1_test(kappa, zeros, ctt, expo, r, s);
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return 0;
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}
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@ -258,6 +258,7 @@ set mips_option_groups {
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madd "HAS_MADD"
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maddps "HAS_MADDPS"
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lsa "(|!)HAS_LSA"
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lxc1 "HAS_LXC1"
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section_start "-Wl,--section-start=.*"
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frame-header "-mframe-header-opt|-mno-frame-header-opt"
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stack-protector "-fstack-protector"
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@ -282,6 +283,7 @@ foreach option {
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gpopt
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local-sdata
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long-calls
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lxc1-sxc1
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paired-single
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plt
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shared
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@ -855,6 +857,12 @@ proc mips-dg-init {} {
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"-mno-smartmips",
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#endif
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#ifdef __mips_no_lxc1_sxc1
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"-mno-lxc1-sxc1",
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#else
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"-mlxc1-sxc1"
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#endif
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#ifdef __mips_synci
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"-msynci",
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#else
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@ -1173,7 +1181,8 @@ proc mips-dg-options { args } {
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#
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#
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} elseif { $isa < 4
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&& [mips_have_test_option_p options "HAS_MOVN"] } {
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&& ([mips_have_test_option_p options "HAS_LXC1"]
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|| [mips_have_test_option_p options "HAS_MOVN"]) } {
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mips_make_test_option options "-mips4"
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# We need MIPS III or higher for:
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#
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@ -1214,6 +1223,7 @@ proc mips-dg-options { args } {
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|| [mips_have_test_option_p options "-mfp32"]
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|| [mips_have_test_option_p options "-mfix-r10000"]
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|| [mips_have_test_option_p options "NOT_HAS_DMUL"]
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|| [mips_have_test_option_p options "HAS_LXC1"]
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|| [mips_have_test_option_p options "HAS_MOVN"]
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|| [mips_have_test_option_p options "HAS_MADD"]
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|| [mips_have_test_option_p options "-mpaired-single"]
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