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sparc.md (*ashrsi3_extend): Rename to...

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* config/sparc/sparc.md (*ashrsi3_extend): Rename to...
	(*ashrsi3_extend0): ...this.  Accept constant integers.
	(*ashrsi3_extend2): Rename to...
	(*ashrsi3_extend1): ...this.
	(*ashrsi3_extend2): New pattern.
	(*lshrsi3_extend1): Accept constant integers.
	(*lshrsi3_extend2): Fix condition on operand 2.

From-SVN: r242753
This commit is contained in:
Eric Botcazou 2016-11-23 13:34:20 +00:00 committed by Eric Botcazou
parent 4987b1e033
commit abe405742f
2 changed files with 45 additions and 11 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2016-11-23 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.md (*ashrsi3_extend): Rename to...
(*ashrsi3_extend0): ...this. Accept constant integers.
(*ashrsi3_extend2): Rename to...
(*ashrsi3_extend1): ...this.
(*ashrsi3_extend2): New pattern.
(*lshrsi3_extend1): Accept constant integers.
(*lshrsi3_extend2): Fix condition on operand 2.
2016-11-23 Martin Liska <mliska@suse.cz>
* config/i386/i386.c: Initialize function pointer to NULL.

46
gcc/config/sparc/sparc.md
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@ -6508,17 +6508,22 @@
}
[(set_attr "type" "shift")])
(define_insn "*ashrsi3_extend"
(define_insn "*ashrsi3_extend0"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "r"))))]
(match_operand:SI 2 "arith_operand" "rI"))))]
"TARGET_ARCH64"
"sra\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sra\t%1, %2, %0";
}
[(set_attr "type" "shift")])
;; This handles the case as above, but with constant shift instead of
;; register. Combiner "simplifies" it for us a little bit though.
(define_insn "*ashrsi3_extend2"
;; This handles the case where
;; (sign_extend:DI (ashiftrt:SI (match_operand:SI) (match_operand:SI)))
;; but combiner "simplifies" it for us.
(define_insn "*ashrsi3_extend1"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
(const_int 32))
@ -6530,6 +6535,21 @@
}
[(set_attr "type" "shift")])
;; This handles the case where
;; (ashiftrt:DI (sign_extend:DI (match_operand:SI)) (const_int))
;; but combiner "simplifies" it for us.
(define_insn "*ashrsi3_extend2"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
(match_operand 2 "small_int_operand" "I")
(const_int 32)))]
"TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32"
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
return "sra\t%1, %2, %0";
}
[(set_attr "type" "shift")])
(define_expand "ashrdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
@ -6595,26 +6615,30 @@
[(set_attr "type" "shift")])
;; This handles the case where
;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI)))
;; but combiner "simplifies" it for us.
(define_insn "*lshrsi3_extend1"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "r")) 0)
(match_operand:SI 2 "arith_operand" "rI")) 0)
(match_operand 3 "const_int_operand" "")))]
"TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff"
"srl\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%1, %2, %0";
}
[(set_attr "type" "shift")])
;; This handles the case where
;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int))
;; but combiner "simplifies" it for us.
(define_insn "*lshrsi3_extend2"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
(match_operand 2 "small_int_operand" "I")
(const_int 32)))]
"TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
"TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32"
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
return "srl\t%1, %2, %0";