mips.md (JOIN_MODE): New mode iterator.
gcc/ * config/mips/mips.md (JOIN_MODE): New mode iterator. (join2_load_Store<JOIN_MODE:mode>): New pattern. (join2_loadhi): Likewise. (define_peehole2): Add peephole2 patterns to join 2 HI/SI/SF/DF-mode load-load and store-stores. * config/mips/mips.opt (mload-store-pairs): New option. (TARGET_LOAD_STORE_PAIRS): New macro. * config/mips/mips.h (ENABLE_LD_ST_PAIRS): Likewise. * config/mips/mips-protos.h (mips_load_store_bonding_p): New prototype. * config/mips/mips.c (mips_load_store_bonding_p): New function. gcc/testsuite/ * gcc.target/mips/p5600-bonding.c : New file. From-SVN: r223334
This commit is contained in:
Prachi Godbole
parent
fab27f5289
commit
abf96035ef
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@ -1,3 +1,16 @@
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2015-05-19 Sameera Deshpande <Sameera.Deshpande@imgtec.com>
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* config/mips/mips.md (JOIN_MODE): New mode iterator.
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(join2_load_Store<JOIN_MODE:mode>): New pattern.
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(join2_loadhi): Likewise.
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(define_peehole2): Add peephole2 patterns to join 2 HI/SI/SF/DF-mode
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load-load and store-stores.
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* config/mips/mips.opt (mload-store-pairs): New option.
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(TARGET_LOAD_STORE_PAIRS): New macro.
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* config/mips/mips.h (ENABLE_LD_ST_PAIRS): Likewise.
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* config/mips/mips-protos.h (mips_load_store_bonding_p): New prototype.
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* config/mips/mips.c (mips_load_store_bonding_p): New function.
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2015-05-19 Mikhail Maltsev <maltsevm@gmail.com>
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* bb-reorder.c (fix_up_fall_thru_edges): Use std::swap instead of
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@ -360,6 +360,7 @@ extern bool mips_epilogue_uses (unsigned int);
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extern void mips_final_prescan_insn (rtx_insn *, rtx *, int);
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extern int mips_trampoline_code_size (void);
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extern void mips_function_profiler (FILE *);
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extern bool mips_load_store_bonding_p (rtx *, machine_mode, bool);
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typedef rtx (*mulsidi3_gen_fn) (rtx, rtx, rtx);
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#ifdef RTX_CODE
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@ -18231,6 +18231,66 @@ umips_load_store_pair_p_1 (bool load_p, bool swap_p,
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return true;
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}
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bool
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mips_load_store_bonding_p (rtx *operands, machine_mode mode, bool load_p)
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{
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rtx reg1, reg2, mem1, mem2, base1, base2;
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enum reg_class rc1, rc2;
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HOST_WIDE_INT offset1, offset2;
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if (load_p)
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{
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reg1 = operands[0];
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reg2 = operands[2];
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mem1 = operands[1];
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mem2 = operands[3];
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}
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else
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{
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reg1 = operands[1];
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reg2 = operands[3];
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mem1 = operands[0];
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mem2 = operands[2];
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}
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if (mips_address_insns (XEXP (mem1, 0), mode, false) == 0
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|| mips_address_insns (XEXP (mem2, 0), mode, false) == 0)
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return false;
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mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
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mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
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/* Base regs do not match. */
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if (!REG_P (base1) || !rtx_equal_p (base1, base2))
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return false;
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/* Either of the loads is clobbering base register. It is legitimate to bond
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loads if second load clobbers base register. However, hardware does not
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support such bonding. */
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if (load_p
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&& (REGNO (reg1) == REGNO (base1)
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|| (REGNO (reg2) == REGNO (base1))))
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return false;
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/* Loading in same registers. */
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if (load_p
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&& REGNO (reg1) == REGNO (reg2))
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return false;
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/* The loads/stores are not of same type. */
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rc1 = REGNO_REG_CLASS (REGNO (reg1));
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rc2 = REGNO_REG_CLASS (REGNO (reg2));
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if (rc1 != rc2
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&& !reg_class_subset_p (rc1, rc2)
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&& !reg_class_subset_p (rc2, rc1))
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return false;
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if (abs (offset1 - offset2) != GET_MODE_SIZE (mode))
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return false;
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return true;
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}
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/* OPERANDS describes the operands to a pair of SETs, in the order
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dest1, src1, dest2, src2. Return true if the operands can be used
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in an LWP or SWP instruction; LOAD_P says which. */
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@ -3162,3 +3162,10 @@ extern GTY(()) struct target_globals *mips16_globals;
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#define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
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#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
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#endif
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/* Load store bonding is not supported by micromips and fix_24k. The
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performance can be degraded for those targets. Hence, do not bond for
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micromips or fix_24k. */
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#define ENABLE_LD_ST_PAIRS \
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(TARGET_LOAD_STORE_PAIRS && TUNE_P5600 \
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&& !TARGET_MICROMIPS && !TARGET_FIX_24K)
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@ -754,6 +754,11 @@
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(define_mode_iterator MOVEP1 [SI SF])
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(define_mode_iterator MOVEP2 [SI SF])
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(define_mode_iterator JOIN_MODE [HI
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SI
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(SF "TARGET_HARD_FLOAT")
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(DF "TARGET_HARD_FLOAT
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&& TARGET_DOUBLE_FLOAT")])
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;; This mode iterator allows :HILO to be used as the mode of the
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;; concatenated HI and LO registers.
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@ -7404,6 +7409,112 @@
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{ return MIPS_CALL ("jal", operands, 0, -1); }
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[(set_attr "type" "call")
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(set_attr "insn_count" "3")])
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;; Match paired HI/SI/SF/DFmode load/stores.
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(define_insn "*join2_load_store<JOIN_MODE:mode>"
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[(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m")
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(match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f"))
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(set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m")
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(match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))]
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"ENABLE_LD_ST_PAIRS && reload_completed"
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{
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bool load_p = (which_alternative == 0 || which_alternative == 1);
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/* Reg-renaming pass reuses base register if it is dead after bonded loads.
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Hardware does not bond those loads, even when they are consecutive.
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However, order of the loads need to be checked for correctness. */
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if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1]))
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{
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output_asm_insn (mips_output_move (operands[0], operands[1]),
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operands);
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output_asm_insn (mips_output_move (operands[2], operands[3]),
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&operands[2]);
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}
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else
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{
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output_asm_insn (mips_output_move (operands[2], operands[3]),
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&operands[2]);
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output_asm_insn (mips_output_move (operands[0], operands[1]),
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operands);
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}
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return "";
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}
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[(set_attr "move_type" "load,fpload,store,fpstore")
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(set_attr "insn_count" "2,2,2,2")])
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;; 2 HI/SI/SF/DF loads are joined.
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;; P5600 does not support bonding of two LBs, hence QI mode is not included.
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;; The loads must be non-volatile as they might be reordered at the time of asm
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;; generation.
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(define_peephole2
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[(set (match_operand:JOIN_MODE 0 "register_operand")
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(match_operand:JOIN_MODE 1 "non_volatile_mem_operand"))
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(set (match_operand:JOIN_MODE 2 "register_operand")
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(match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))]
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"ENABLE_LD_ST_PAIRS
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&& mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)"
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[(parallel [(set (match_dup 0)
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(match_dup 1))
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(set (match_dup 2)
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(match_dup 3))])]
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"")
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;; 2 HI/SI/SF/DF stores are joined.
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;; P5600 does not support bonding of two SBs, hence QI mode is not included.
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(define_peephole2
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[(set (match_operand:JOIN_MODE 0 "memory_operand")
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(match_operand:JOIN_MODE 1 "register_operand"))
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(set (match_operand:JOIN_MODE 2 "memory_operand")
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(match_operand:JOIN_MODE 3 "register_operand"))]
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"ENABLE_LD_ST_PAIRS
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&& mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)"
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[(parallel [(set (match_dup 0)
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(match_dup 1))
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(set (match_dup 2)
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(match_dup 3))])]
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"")
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;; Match paired HImode loads.
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(define_insn "*join2_loadhi"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m")))
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(set (match_operand:SI 2 "register_operand" "=r")
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(any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))]
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"ENABLE_LD_ST_PAIRS && reload_completed"
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{
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/* Reg-renaming pass reuses base register if it is dead after bonded loads.
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Hardware does not bond those loads, even when they are consecutive.
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However, order of the loads need to be checked for correctness. */
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if (!reg_overlap_mentioned_p (operands[0], operands[1]))
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{
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output_asm_insn ("lh<u>\t%0,%1", operands);
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output_asm_insn ("lh<u>\t%2,%3", operands);
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}
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else
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{
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output_asm_insn ("lh<u>\t%2,%3", operands);
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output_asm_insn ("lh<u>\t%0,%1", operands);
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}
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return "";
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}
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[(set_attr "move_type" "load")
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(set_attr "insn_count" "2")])
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;; 2 HI loads are joined.
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand")
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(any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand")))
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(set (match_operand:SI 2 "register_operand")
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(any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))]
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"ENABLE_LD_ST_PAIRS
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&& mips_load_store_bonding_p (operands, HImode, true)"
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[(parallel [(set (match_dup 0)
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(any_extend:SI (match_dup 1)))
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(set (match_dup 2)
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(any_extend:SI (match_dup 3)))])]
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"")
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;; Synchronization instructions.
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@ -418,3 +418,7 @@ Enable use of odd-numbered single-precision registers
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noasmopt
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Driver
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mload-store-pairs
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Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1)
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Enable load/store bonding.
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@ -1,3 +1,7 @@
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2015-05-19 Sameera Deshpande <sameera.deshpande@imgtec.com>
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* gcc.target/mips/p5600-bonding.c : New file.
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2015-05-18 Steven G. Kargl <kargl@gcc.gnu.org>
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PR fortran/66106
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@ -0,0 +1,20 @@
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/* { dg-do compile } */
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/* { dg-options "-dp -mtune=p5600 -mno-micromips -mno-mips16" } */
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/* { dg-skip-if "Bonding needs peephole optimization." { *-*-* } { "-O0" "-O1" } { "" } } */
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typedef int VINT32 __attribute__ ((vector_size((16))));
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void
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memory_operation (void * __restrict src, void * __restrict dest, int num)
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{
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VINT32 *vsrc = (VINT32 *) src;
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VINT32 *vdest = (VINT32 *) dest;
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int i;
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for (i = 0; i < num - 1; i += 2)
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{
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vdest[i] = vdest[i] + vsrc[i];
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vdest[i + 1] = vdest[i + 1] + vsrc[i + 1];
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}
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}
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/* { dg-final { scan-assembler "join2_" } } */
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