OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

PR target/83009: Relax strict address checking for store pair lanes

Browse Source 
The operand constraint for the memory address of store/load pair lanes was
enforcing strictly hardware registers be allowed as memory addresses.  We want
to relax that such that these patterns can be used by combine.  During register
allocation the register constraint will enforce the correct register is chosen.

gcc
2018-05-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/83009
	* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
	address check not strict.

gcc/testsuite
2018-05-24  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR target/83009
	* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.

From-SVN: r260635
This commit is contained in:
Andre Vieira 2018-05-24 08:53:39 +00:00 committed by Andre Vieira
parent 5d75ad95aa
commit ac025fd6cb
4 changed files with 37 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
address check not strict.
2018-05-24 Richard Sandiford <richard.sandiford@linaro.org>
* gimple-match.h (gimple_match_op): New class.

2
gcc/config/aarch64/predicates.md
View File

@ -226,7 +226,7 @@
;; as a 128-bit vec_concat.
(define_predicate "aarch64_mem_pair_lanes_operand"
(and (match_code "mem")
(match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
(match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), false,
ADDR_QUERY_LDP_STP)")))
(define_predicate "aarch64_prefetch_operand"

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
2018-05-23 Jozef Lawrynowicz <jozef.l@somniumtech.com>
PR target/78849

28
gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c
View File

@ -22,10 +22,32 @@ construct_lane_2 (long long *y, v2di *z)
z[2] = x;
}
void
construct_lane_3 (double **py, v2df **pz)
{
double *y = *py;
v2df *z = *pz;
double y0 = y[0] + 1;
double y1 = y[1] + 2;
v2df x = {y0, y1};
z[2] = x;
}
void
construct_lane_4 (long long **py, v2di **pz)
{
long long *y = *py;
v2di *z = *pz;
long long y0 = y[0] + 1;
long long y1 = y[1] + 2;
v2di x = {y0, y1};
z[2] = x;
}
/* We can use the load_pair_lanes<mode> pattern to vec_concat two DI/DF
values from consecutive memory into a 2-element vector by using
a Q-reg LDR. */
/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 { xfail ilp32 } } } */
/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 { xfail ilp32 } } } */
/* { dg-final { scan-assembler-not "ins\t" { xfail ilp32 } } } */
/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 2 } } */
/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 2 } } */
/* { dg-final { scan-assembler-not "ins\t" } } */