s390-protos.h (shift_count_operand): Add prototype.
* config/s390/s390-protos.h (shift_count_operand): Add prototype. * config/s390/s390.c (shift_count_operand): New function. (s390_extra_constraint): Use it to implement 'Y' constraint. (print_shift_count_operand): New function. (print_operand): Use it to implement '%Y'. * config/s390/s390.h (EXTRA_ADDRESS_CONSTRAINT): Add 'Y' constraint. (PREDICATE_CODES): Add shift_count_operand. * config/s390/s390.md ("rotldi3"): Merge alternatives, using "shift_count_operand" predicate and "Y" constraint, and "%Y" to output the combined shift count. ("rotlsi3"): Likewise. ("ashldi3", "*ashldi3_31", "*ashldi3_64"): Likewise. ("ashrdi3", "*ashrdi3_31", "*ashrdi3_64", "*ashrdi3_cc_31", "*ashrdi3_cc_64", "*ashrdi3_cconly_31", "*ashrdi3_cconly_64"): Likewise. ("ashlsi3", "ashrsi3", "*ashrsi3_cc", "*ashrsi3_cconly"): Likewise. ("lshrdi3", "*lshrdi3_31", "*lshrdi3_64"): Likewise. ("lshrsi3"): Likewise. From-SVN: r72661
This commit is contained in:
parent
3f12a2e0b4
commit
ac32b25eb8
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@ -1,3 +1,23 @@
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2003-10-18 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390-protos.h (shift_count_operand): Add prototype.
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* config/s390/s390.c (shift_count_operand): New function.
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(s390_extra_constraint): Use it to implement 'Y' constraint.
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(print_shift_count_operand): New function.
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(print_operand): Use it to implement '%Y'.
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* config/s390/s390.h (EXTRA_ADDRESS_CONSTRAINT): Add 'Y' constraint.
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(PREDICATE_CODES): Add shift_count_operand.
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* config/s390/s390.md ("rotldi3"): Merge alternatives,
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using "shift_count_operand" predicate and "Y" constraint,
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and "%Y" to output the combined shift count.
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("rotlsi3"): Likewise.
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("ashldi3", "*ashldi3_31", "*ashldi3_64"): Likewise.
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("ashrdi3", "*ashrdi3_31", "*ashrdi3_64", "*ashrdi3_cc_31",
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"*ashrdi3_cc_64", "*ashrdi3_cconly_31", "*ashrdi3_cconly_64"): Likewise.
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("ashlsi3", "ashrsi3", "*ashrsi3_cc", "*ashrsi3_cconly"): Likewise.
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("lshrdi3", "*lshrdi3_31", "*lshrdi3_64"): Likewise.
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("lshrsi3"): Likewise.
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2003-10-18 Gunther Nikl <gni@gecko.de>
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* config/m68k/m68k.c (m68k_output_function_epilogue): Add missing
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@ -36,6 +36,7 @@ extern int consttable_operand (rtx, enum machine_mode);
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extern int larl_operand (rtx, enum machine_mode);
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extern int s_operand (rtx, enum machine_mode);
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extern int s_imm_operand (rtx, enum machine_mode);
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extern int shift_count_operand (rtx, enum machine_mode);
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extern int bras_sym_operand (rtx, enum machine_mode);
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extern int load_multiple_operation (rtx, enum machine_mode);
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extern int store_multiple_operation (rtx, enum machine_mode);
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@ -211,6 +211,7 @@ static int s390_short_displacement (rtx);
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static int s390_decompose_address (rtx, struct s390_address *);
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static rtx get_thread_pointer (void);
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static rtx legitimize_tls_address (rtx, rtx);
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static void print_shift_count_operand (FILE *, rtx);
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static const char *get_some_local_dynamic_name (void);
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static int get_some_local_dynamic_name_1 (rtx *, void *);
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static int reg_used_in_mem_p (int, rtx);
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@ -1274,6 +1275,45 @@ s_imm_operand (register rtx op, enum machine_mode mode)
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return general_s_operand (op, mode, 1);
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}
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/* Return true if OP a valid shift count operand.
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OP is the current operation.
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MODE is the current operation mode. */
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int
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shift_count_operand (rtx op, enum machine_mode mode)
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{
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HOST_WIDE_INT offset = 0;
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if (! check_mode (op, &mode))
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return 0;
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/* We can have an integer constant, an address register,
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or a sum of the two. Note that reload already checks
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that any register present is an address register, so
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we just check for any register here. */
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if (GET_CODE (op) == CONST_INT)
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{
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offset = INTVAL (op);
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op = NULL_RTX;
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}
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if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
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{
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offset = INTVAL (XEXP (op, 1));
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op = XEXP (op, 0);
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}
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while (op && GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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if (op && GET_CODE (op) != REG)
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return 0;
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/* Unfortunately we have to reject constants that are invalid
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for an address, or else reload will get confused. */
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if (!DISP_IN_RANGE (offset))
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return 0;
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return 1;
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}
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/* Return true if DISP is a valid short displacement. */
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static int
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@ -1383,6 +1423,9 @@ s390_extra_constraint (rtx op, int c)
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return 0;
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break;
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case 'Y':
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return shift_count_operand (op, VOIDmode);
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default:
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return 0;
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}
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@ -3281,6 +3324,40 @@ s390_delegitimize_address (rtx orig_x)
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return orig_x;
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}
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/* Output shift count operand OP to stdio stream FILE. */
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static void
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print_shift_count_operand (FILE *file, rtx op)
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{
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HOST_WIDE_INT offset = 0;
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/* We can have an integer constant, an address register,
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or a sum of the two. */
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if (GET_CODE (op) == CONST_INT)
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{
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offset = INTVAL (op);
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op = NULL_RTX;
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}
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if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
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{
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offset = INTVAL (XEXP (op, 1));
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op = XEXP (op, 0);
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}
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while (op && GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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/* Sanity check. */
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if (op && (GET_CODE (op) != REG
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|| REGNO (op) >= FIRST_PSEUDO_REGISTER
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|| REGNO_REG_CLASS (REGNO (op)) != ADDR_REGS))
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abort ();
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/* Shift counts are truncated to the low six bits anyway. */
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & 63);
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if (op)
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fprintf (file, "(%s)", reg_names[REGNO (op)]);
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}
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/* Locate some local-dynamic symbol still in use by this function
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so that we can print its name in local-dynamic base patterns. */
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@ -3451,6 +3528,7 @@ print_operand_address (FILE *file, rtx addr)
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'R': print only the base register of a memory reference.
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'N': print the second word of a DImode operand.
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'M': print the second word of a TImode operand.
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'Y': print shift count operand.
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'b': print integer X as if it's an unsigned byte.
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'x': print integer X as if it's an unsigned word.
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@ -3540,6 +3618,10 @@ print_operand (FILE *file, rtx x, int code)
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else
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abort ();
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break;
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case 'Y':
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print_shift_count_operand (file, x);
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return;
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}
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switch (GET_CODE (x))
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@ -544,7 +544,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
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#define EXTRA_MEMORY_CONSTRAINT(C, STR) \
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((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
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#define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
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((C) == 'U' || (C) == 'W')
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((C) == 'U' || (C) == 'W' || (C) == 'Y')
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/* Stack layout and calling conventions. */
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@ -1023,6 +1023,7 @@ do { \
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#define PREDICATE_CODES \
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{"s_operand", { SUBREG, MEM }}, \
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{"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
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{"shift_count_operand", { REG, SUBREG, PLUS, CONST_INT }}, \
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{"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
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{"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
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{"load_multiple_operation", {PARALLEL}}, \
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@ -5982,13 +5982,11 @@
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;
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(define_insn "rotldi3"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(rotate:DI (match_operand:DI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))]
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[(set (match_operand:DI 0 "register_operand" "=d")
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(rotate:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y")))]
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"TARGET_64BIT"
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"@
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rllg\t%0,%1,%c2
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rllg\t%0,%1,0(%2)"
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"rllg\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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@ -5997,13 +5995,11 @@
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;
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(define_insn "rotlsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))]
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[(set (match_operand:SI 0 "register_operand" "=d")
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(rotate:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y")))]
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"TARGET_CPU_ZARCH"
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"@
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rll\t%0,%1,%c2
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rll\t%0,%1,0(%2)"
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"rll\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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@ -6019,29 +6015,25 @@
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(define_expand "ashldi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(ashift:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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(match_operand:SI 2 "shift_count_operand" "")))]
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""
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"")
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(define_insn "*ashldi3_31"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(ashift:DI (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))]
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashift:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_operand" "Y")))]
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"!TARGET_64BIT"
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"@
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sldl\t%0,%c2
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sldl\t%0,0(%2)"
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"sldl\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashldi3_64"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))]
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashift:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y")))]
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"TARGET_64BIT"
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"@
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sllg\t%0,%1,%2
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sllg\t%0,%1,0(%2)"
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"sllg\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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@ -6053,86 +6045,74 @@
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[(parallel
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[(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))
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(match_operand:SI 2 "shift_count_operand" "")))
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(clobber (reg:CC 33))])]
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""
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"")
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(define_insn "*ashrdi3_cc_31"
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[(set (reg 33)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "J,a"))
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_operand" "Y"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d,d")
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(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_dup 1) (match_dup 2)))]
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"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
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"@
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srda\t%0,%c2
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srda\t%0,0(%2)"
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"srda\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cconly_31"
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[(set (reg 33)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "J,a"))
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_operand" "Y"))
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(const_int 0)))
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(clobber (match_scratch:DI 0 "=d,d"))]
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(clobber (match_scratch:DI 0 "=d"))]
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"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
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"@
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srda\t%0,%c2
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srda\t%0,0(%2)"
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"srda\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_31"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:SI 2 "shift_count_operand" "Y")))
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"@
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srda\t%0,%c2
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srda\t%0,0(%2)"
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"srda\t%0,%Y2"
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[(set_attr "op_type" "RS")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cc_64"
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[(set (reg 33)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a"))
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y"))
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(const_int 0)))
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(set (match_operand:DI 0 "register_operand" "=d,d")
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(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
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"@
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srag\t%0,%1,%c2
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srag\t%0,%1,0(%2)"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_cconly_64"
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[(set (reg 33)
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a"))
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(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y"))
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(const_int 0)))
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(clobber (match_scratch:DI 0 "=d,d"))]
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(clobber (match_scratch:DI 0 "=d"))]
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"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
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"@
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srag\t%0,%1,%c2
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srag\t%0,%1,0(%2)"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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(define_insn "*ashrdi3_64"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
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(match_operand:SI 2 "nonmemory_operand" "J,a")))
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:SI 2 "shift_count_operand" "Y")))
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"@
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srag\t%0,%1,%c2
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srag\t%0,%1,0(%2)"
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"srag\t%0,%1,%Y2"
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[(set_attr "op_type" "RSE")
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(set_attr "atype" "reg")])
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|
@ -6142,13 +6122,11 @@
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;
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(define_insn "ashlsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(ashift:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y")))]
|
||||
""
|
||||
"@
|
||||
sll\t%0,%c2
|
||||
sll\t%0,0(%2)"
|
||||
"sll\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
|
@ -6158,41 +6136,35 @@
|
|||
|
||||
(define_insn "*ashrsi3_cc"
|
||||
[(set (reg 33)
|
||||
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a"))
|
||||
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "register_operand" "=d,d")
|
||||
(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
||||
"s390_match_ccmode(insn, CCSmode)"
|
||||
"@
|
||||
sra\t%0,%c2
|
||||
sra\t%0,0(%2)"
|
||||
"sra\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
|
||||
(define_insn "*ashrsi3_cconly"
|
||||
[(set (reg 33)
|
||||
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a"))
|
||||
(compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=d,d"))]
|
||||
(clobber (match_scratch:SI 0 "=d"))]
|
||||
"s390_match_ccmode(insn, CCSmode)"
|
||||
"@
|
||||
sra\t%0,%c2
|
||||
sra\t%0,0(%2)"
|
||||
"sra\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
(define_insn "ashrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
||||
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a")))
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y")))
|
||||
(clobber (reg:CC 33))]
|
||||
""
|
||||
"@
|
||||
sra\t%0,%c2
|
||||
sra\t%0,0(%2)"
|
||||
"sra\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
|
@ -6208,30 +6180,26 @@
|
|||
(define_expand "lshrdi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "nonmemory_operand" "")))]
|
||||
(match_operand:SI 2 "shift_count_operand" "")))]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_insn "*lshrdi3_31"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
||||
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y")))]
|
||||
"!TARGET_64BIT"
|
||||
"@
|
||||
srdl\t%0,%c2
|
||||
srdl\t%0,0(%2)"
|
||||
[(set_attr "op_type" "RS,RS")
|
||||
"srdl\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
(define_insn "*lshrdi3_64"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
||||
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y")))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
srlg\t%0,%1,%c2
|
||||
srlg\t%0,%1,0(%2)"
|
||||
[(set_attr "op_type" "RSE,RSE")
|
||||
"srlg\t%0,%1,%Y2"
|
||||
[(set_attr "op_type" "RSE")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
;
|
||||
|
@ -6239,13 +6207,11 @@
|
|||
;
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "shift_count_operand" "Y")))]
|
||||
""
|
||||
"@
|
||||
srl\t%0,%c2
|
||||
srl\t%0,0(%2)"
|
||||
"srl\t%0,%Y2"
|
||||
[(set_attr "op_type" "RS")
|
||||
(set_attr "atype" "reg")])
|
||||
|
||||
|
|
Loading…
Reference in New Issue