darwin.md: Delete the altivec patterns which are handled differently now.
2004-08-18 Andrew Pinski <apinski@apple.com>
* config/rs6000/darwin.md: Delete the altivec patterns which are
handled differently now.
(load_macho_picbase_di): Make sure that is only happens for TARGET_64BIT
(macho_correct_pic_di): Likewise.
(call_indirect_nonlocal_darwin64): Likewise.
Delete the save world/saveFP/saveVec patterns.
Revert the reversion of: 2004-08-16 Stan Shebs <shebs@apple.com>
* config/darwin.c (macho_indirect_data_reference): Add DImode case.
* config/rs6000/rs6000.md: Include darwin.md.
(builtin_setjmp_receiver): Add DImode case.
* config/rs6000/rs6000.c (rs6000_emit_move): Add DImode case to
Darwin bits.
From-SVN: r86204
This commit is contained in:
Andrew Pinski
Andrew Pinski
parent
92b9a671bf
commit
ac9e2cff8d
@ -1,3 +1,19 @@
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2004-08-18 Andrew Pinski <apinski@apple.com>
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* config/rs6000/darwin.md: Delete the altivec patterns which are
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handled differently now.
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(load_macho_picbase_di): Make sure that is only happens for TARGET_64BIT
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(macho_correct_pic_di): Likewise.
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(call_indirect_nonlocal_darwin64): Likewise.
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Delete the save world/saveFP/saveVec patterns.
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Revert the reversion of: 2004-08-16 Stan Shebs <shebs@apple.com>
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* config/darwin.c (macho_indirect_data_reference): Add DImode case.
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* config/rs6000/rs6000.md: Include darwin.md.
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(builtin_setjmp_receiver): Add DImode case.
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* config/rs6000/rs6000.c (rs6000_emit_move): Add DImode case to
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Darwin bits.
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2004-08-18 Matt Austern <austern@apple.com>
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Dead code stripping
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@ -62,8 +78,8 @@
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2004-08-18 Andrew Pinski <apinski@apple.com>
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* config/darwin.c (machopic_legitimize_pic_address): Only set MEM_READONLY_P
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in the non TARGET_TOC case.
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* config/darwin.c (machopic_legitimize_pic_address): Only set
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MEM_READONLY_P in the non TARGET_TOC case.
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2004-08-18 Zack Weinberg <zack@codesourcery.com>
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@ -333,8 +333,12 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
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if (defined && MACHO_DYNAMIC_NO_PIC_P)
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{
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#if defined (TARGET_TOC)
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emit_insn (gen_macho_high (reg, orig));
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emit_insn (gen_macho_low (reg, reg, orig));
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emit_insn (GET_MODE (orig) == DImode
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? gen_macho_high_di (reg, orig)
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: gen_macho_high (reg, orig));
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emit_insn (GET_MODE (orig) == DImode
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? gen_macho_low_di (reg, reg, orig)
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: gen_macho_low (reg, reg, orig));
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#else
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/* some other cpu -- writeme! */
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abort ();
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@ -529,7 +533,9 @@ machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
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rtx asym = XEXP (orig, 0);
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rtx mem;
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emit_insn (gen_macho_high (temp_reg, asym));
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emit_insn (mode == DImode
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? gen_macho_high_di (temp_reg, asym)
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: gen_macho_high (temp_reg, asym));
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mem = gen_rtx_MEM (GET_MODE (orig),
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gen_rtx_LO_SUM (Pmode, temp_reg, asym));
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MEM_READONLY_P (mem) = 1;
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@ -145,55 +145,10 @@ Boston, MA 02111-1307, USA. */
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(match_dup 2))]
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"")
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(define_insn ""
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[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "b,r")
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(match_operand:DI 1 "gpc_reg_operand" "r,b")))
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(match_operand:V4SI 2 "register_operand" "v,v"))]
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"TARGET_MACHO && TARGET_64BIT"
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"@
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stvx %2,%0,%1
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stvx %2,%1,%0"
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[(set_attr "type" "vecstore")])
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(define_insn ""
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[(set (mem:V4SI (match_operand:DI 0 "gpc_reg_operand" "r"))
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(match_operand:V4SI 1 "register_operand" "v"))]
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"TARGET_MACHO && TARGET_64BIT"
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"stvx %1,0,%0"
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[(set_attr "type" "vecstore")])
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(define_split
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[(set (match_operand:V4SI 0 "register_operand" "")
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(mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "short_cint_operand" ""))))
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(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
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"TARGET_MACHO && TARGET_64BIT"
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[(set (match_dup 3) (plus:DI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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(mem:V4SI (match_dup 3)))]
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"")
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(define_insn ""
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[(set (match_operand:V4SI 0 "register_operand" "=v,v")
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(mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b,r")
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(match_operand:DI 2 "gpc_reg_operand" "r,b"))))]
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"TARGET_MACHO && TARGET_64BIT"
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"@
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lvx %0,%1,%2
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lvx %0,%2,%1"
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[(set_attr "type" "vecload")])
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(define_insn ""
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(mem:V4SI (match_operand:DI 1 "gpc_reg_operand" "r")))]
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"TARGET_MACHO && TARGET_64BIT"
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"lvx %0,0,%1"
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[(set_attr "type" "vecload")])
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(define_insn "load_macho_picbase_di"
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[(set (match_operand:DI 0 "register_operand" "=l")
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(unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] 15))]
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
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"bcl 20,31,%1\\n%1:"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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@ -204,7 +159,7 @@ Boston, MA 02111-1307, USA. */
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(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
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(match_operand:DI 3 "immediate_operand" "s")]
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16)))]
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"DEFAULT_ABI == ABI_DARWIN"
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"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
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"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
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[(set_attr "length" "8")])
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@ -213,7 +168,7 @@ Boston, MA 02111-1307, USA. */
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(match_operand 1 "" "g,g,g,g"))
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(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
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(clobber (match_scratch:SI 3 "=l,l,l,l"))]
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"DEFAULT_ABI == ABI_DARWIN"
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"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
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{
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return "b%T0l";
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}
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@ -338,59 +293,3 @@ Boston, MA 02111-1307, USA. */
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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(define_insn "*save_fpregs_with_label_di"
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[(match_parallel 0 "any_operand"
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[(clobber (match_operand:DI 1 "register_operand" "=l"))
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(use (match_operand:DI 2 "call_operand" "s"))
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(use (match_operand:DI 3 "" ""))
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(set (match_operand:DF 4 "memory_operand" "=m")
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(match_operand:DF 5 "gpc_reg_operand" "f"))])]
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"TARGET_64BIT"
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"*
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#if TARGET_MACHO
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const char *picbase = machopic_function_base_name ();
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operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
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#endif
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return \"bl %z2\\n%3:\";
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"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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(define_insn "*save_vregs_di"
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[(match_parallel 0 "any_operand"
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[(clobber (match_operand:DI 1 "register_operand" "=l"))
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(use (match_operand:DI 2 "call_operand" "s"))
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(set (match_operand:V4SI 3 "any_operand" "=m")
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(match_operand:V4SI 4 "register_operand" "v"))])]
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"TARGET_64BIT"
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"bl %z2"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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(define_insn "*restore_vregs_di"
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[(match_parallel 0 "any_operand"
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[(clobber (match_operand:DI 1 "register_operand" "=l"))
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(use (match_operand:DI 2 "call_operand" "s"))
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(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
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(set (match_operand:V4SI 4 "register_operand" "=v")
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(match_operand:V4SI 5 "any_operand" "m"))])]
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"TARGET_64BIT"
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"bl %z2")
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(define_insn "*save_vregs_with_label_di"
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[(match_parallel 0 "any_operand"
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[(clobber (match_operand:DI 1 "register_operand" "=l"))
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(use (match_operand:DI 2 "call_operand" "s"))
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(use (match_operand:DI 3 "" ""))
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(set (match_operand:V4SI 4 "any_operand" "=m")
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(match_operand:V4SI 5 "register_operand" "v"))])]
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"TARGET_64BIT"
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"*
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#if TARGET_MACHO
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const char *picbase = machopic_function_base_name ();
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operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
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#endif
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return \"bl %z2\\n%3:\";
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"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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@ -4322,8 +4322,16 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
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return;
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}
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#endif
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emit_insn (gen_macho_high (target, operands[1]));
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emit_insn (gen_macho_low (operands[0], target, operands[1]));
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if (mode == DImode)
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{
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emit_insn (gen_macho_high_di (target, operands[1]));
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emit_insn (gen_macho_low_di (operands[0], target, operands[1]));
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}
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else
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{
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emit_insn (gen_macho_high (target, operands[1]));
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emit_insn (gen_macho_low (operands[0], target, operands[1]));
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}
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return;
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}
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@ -101,6 +101,7 @@
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(include "8540.md")
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(include "power4.md")
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(include "power5.md")
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(include "darwin.md")
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;; Start with fixed-point load and store insns. Here we put only the more
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@ -10158,8 +10159,12 @@
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CODE_LABEL_NUMBER (operands[0]));
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tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
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emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
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emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
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emit_insn (TARGET_64BIT
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? gen_load_macho_picbase_di (picreg, tmplabrtx)
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: gen_load_macho_picbase (picreg, tmplabrtx));
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emit_insn (TARGET_64BIT
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? gen_macho_correct_pic_di (picreg, picreg, picrtx, tmplabrtx)
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: gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
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}
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else
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#endif
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