diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f81f01d91f0..c13028913b1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -15,6 +15,11 @@
 	* config/ia64/ia64.c (ia64_sched_reorder): Defer scheduling of
 	asms if other insns are available.
 
+	* config/ia64/ia64.c (condop_operator): New predicate.
+	* config/ia64/ia64.h (PREDICATE_CODES): Add it.
+	* config/ia64/ia64.md (cond_opsi2_internal and splitters): New
+	patterns.
+
 2001-08-04  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	* config/sh/sh.c (sh_asm_named_section): Fix typo in align
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 8ff1c8fc201..ce17c91dc3f 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -719,6 +719,19 @@ predicate_operator (op, mode)
 	  && (code == EQ || code == NE));
 }
 
+/* Return 1 if this operator can be used in a conditional operation.  */
+
+int
+condop_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+  return ((GET_MODE (op) == mode || mode == VOIDmode)
+	  && (code == PLUS || code == MINUS || code == AND
+	      || code == IOR || code == XOR));
+}
+
 /* Return 1 if this is the ar.lc register.  */
 
 int
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index b5fe7ef88a5..f6b46938f8e 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -2664,6 +2664,7 @@ do {									\
 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}},			\
 { "signed_inequality_operator", {GE, GT, LE, LT}},			\
 { "predicate_operator", {NE, EQ}},					\
+{ "condop_operator", {PLUS, MINUS, IOR, XOR, AND}},			\
 { "ar_lc_reg_operand", {REG}},						\
 { "ar_ccv_reg_operand", {REG}},						\
 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}},		\
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index f40cc404229..3590630f192 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -4495,6 +4495,82 @@
 				VOIDmode, operands[1], const0_rtx);
 }")
 
+(define_insn "*cond_opsi2_internal"
+  [(set (match_operand:SI 0 "gr_register_operand" "=r")
+	(match_operator:SI 5 "condop_operator"
+	  [(if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "c")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "r")
+	     (match_operand:SI 3 "gr_register_operand" "r"))
+	   (match_operand:SI 4 "gr_register_operand" "r")]))]
+  ""
+  "#"
+  [(set_attr "itanium_class" "ialu")
+   (set_attr "predicable" "no")])
+
+(define_split
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(match_operator:SI 5 "condop_operator"
+	  [(if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "")
+	     (match_operand:SI 3 "gr_register_operand" ""))
+	   (match_operand:SI 4 "gr_register_operand" "")]))]
+  "reload_completed"
+  [(cond_exec
+     (match_dup 6)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
+   (cond_exec
+     (match_dup 7)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
+  "
+{
+  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
+				VOIDmode, operands[1], const0_rtx);
+}")
+
+(define_insn "*cond_opsi2_internal_b"
+  [(set (match_operand:SI 0 "gr_register_operand" "=r")
+	(match_operator:SI 5 "condop_operator"
+	  [(match_operand:SI 4 "gr_register_operand" "r")
+	   (if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "c")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "r")
+	     (match_operand:SI 3 "gr_register_operand" "r"))]))]
+  ""
+  "#"
+  [(set_attr "itanium_class" "ialu")
+   (set_attr "predicable" "no")])
+
+(define_split
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(match_operator:SI 5 "condop_operator"
+	  [(match_operand:SI 4 "gr_register_operand" "")
+	   (if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "")
+	     (match_operand:SI 3 "gr_register_operand" ""))]))]
+  "reload_completed"
+  [(cond_exec
+     (match_dup 6)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
+   (cond_exec
+     (match_dup 7)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
+  "
+{
+  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
+				VOIDmode, operands[1], const0_rtx);
+}")
+
 
 ;; ::::::::::::::::::::
 ;; ::