rs6000: Documentation updates for "future" rename
2020-06-29 Segher Boessenkool <segher@kernel.crashing.org> * doc/extend.texi: Change references to "future architecture" to "ISA 3.1", "-mcpu=future" to "-mcpu=power10", and remove vaguer references to "future" (because the future is now).
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Segher Boessenkool
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@ -17091,7 +17091,7 @@ implementing assertions.
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* Basic PowerPC Built-in Functions Available on ISA 2.06::
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* Basic PowerPC Built-in Functions Available on ISA 2.07::
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* Basic PowerPC Built-in Functions Available on ISA 3.0::
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* Basic PowerPC Built-in Functions Available for a Future Architecture::
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* Basic PowerPC Built-in Functions Available on ISA 3.1::
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@end menu
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This section describes PowerPC built-in functions that do not require
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@ -17651,25 +17651,23 @@ the FPSCR. The instruction is a lower latency version of the @code{mffs}
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instruction. If the @code{mffsl} instruction is not available, then the
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builtin uses the older @code{mffs} instruction to read the FPSCR.
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@node Basic PowerPC Built-in Functions Available for a Future Architecture
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@subsubsection Basic PowerPC Built-in Functions Available for a Future Architecture
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@node Basic PowerPC Built-in Functions Available on ISA 3.1
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@subsubsection Basic PowerPC Built-in Functions Available on ISA 3.1
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The basic built-in functions described in this section are
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available on the PowerPC family of processors starting with a
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hypothetical CPU which may or may not be available in the future, as
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requested by specifying @option{-mcpu=future} on the command line.
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Unless explicitly disabled on the command line,
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specifying @option{-mcpu=future} has the effect of enabling all the
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same options as for @option{-mcpu=power9}.
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available on the PowerPC family of processors starting with ISA 3.1.
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Unless specific options are explicitly disabled on the
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command line, specifying option @option{-mcpu=power10} has the effect of
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enabling all the same options as for @option{-mcpu=power9}.
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The following built-in functions are available on Linux 64-bit systems
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that use a future architecture instruction set (@option{-mcpu=future}):
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that use a future architecture instruction set (@option{-mcpu=power10}):
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@smallexample
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@exdent unsigned long long int
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@exdent __builtin_cfuged (unsigned long long int, unsigned long long int)
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@end smallexample
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Perform a 64-bit centrifuge operation, as if implemented by the Future
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Perform a 64-bit centrifuge operation, as if implemented by the
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@code{cfuged} instruction.
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@findex __builtin_cfuged
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@ -17678,7 +17676,7 @@ Perform a 64-bit centrifuge operation, as if implemented by the Future
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@exdent __builtin_cntlzdm (unsigned long long int, unsigned long long int)
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@end smallexample
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Perform a 64-bit count leading zeros operation under mask, as if
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implemented by the future @code{cntlzdm} instruction.
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implemented by the @code{cntlzdm} instruction.
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@findex __builtin_cntlzdm
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@smallexample
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@ -17686,7 +17684,7 @@ implemented by the future @code{cntlzdm} instruction.
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@exdent __builtin_cnttzdm (unsigned long long int, unsigned long long int)
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@end smallexample
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Perform a 64-bit count trailing zeros operation under mask, as if
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implemented by the future @code{cnttzdm} instruction.
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implemented by the @code{cnttzdm} instruction.
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@findex __builtin_cnttzdm
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@smallexample
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@ -17694,7 +17692,7 @@ implemented by the future @code{cnttzdm} instruction.
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@exdent __builtin_pdepd (unsigned long long int, unsigned long long int)
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@end smallexample
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Perform a 64-bit parallel bits deposit operation, as if implemented by the
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Future @code{pdepd} instruction.
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@code{pdepd} instruction.
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@findex __builtin_pdepd
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@smallexample
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@ -17702,7 +17700,7 @@ Future @code{pdepd} instruction.
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@exdent __builtin_pextd (unsigned long long int, unsigned long long int)
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@end smallexample
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Perform a 64-bit parallel bits extract operation, as if implemented by the
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Future @code{pextd} instruction.
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@code{pextd} instruction.
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@findex __builtin_pextd
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@node PowerPC AltiVec/VSX Built-in Functions
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@ -17816,7 +17814,7 @@ briefly described below.
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* PowerPC AltiVec Built-in Functions Available on ISA 2.06::
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* PowerPC AltiVec Built-in Functions Available on ISA 2.07::
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* PowerPC AltiVec Built-in Functions Available on ISA 3.0::
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* PowerPC AltiVec Built-in Functions Available for a Future Architecture::
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* PowerPC AltiVec Built-in Functions Available on ISA 3.1::
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@end menu
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@node PowerPC AltiVec Built-in Functions on ISA 2.05
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@ -20860,20 +20858,18 @@ void vec_xst (vector unsigned char, int, vector unsigned char *);
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void vec_xst (vector unsigned char, int, unsigned char *);
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@end smallexample
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@node PowerPC AltiVec Built-in Functions Available for a Future Architecture
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@subsubsection PowerPC AltiVec Built-in Functions Available for a Future Architecture
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@node PowerPC AltiVec Built-in Functions Available on ISA 3.1
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@subsubsection PowerPC AltiVec Built-in Functions Available on ISA 3.1
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The following additional built-in functions are also available for the
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PowerPC family of processors, starting with a hypothetical CPU
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which may or may not be available in the future
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(@option{-mcpu=future}) or later:
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PowerPC family of processors, starting with ISA 3.1 (@option{-mcpu=power10}):
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@smallexample
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@exdent vector unsigned long long int
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@exdent vec_cfuge (vector unsigned long long int, vector unsigned long long int)
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@end smallexample
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Perform a vector centrifuge operation, as if implemented by the Future
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Perform a vector centrifuge operation, as if implemented by the
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@code{vcfuged} instruction.
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@findex vec_cfuge
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@ -20882,7 +20878,7 @@ Perform a vector centrifuge operation, as if implemented by the Future
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@exdent vec_cntlzm (vector unsigned long long int, vector unsigned long long int)
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@end smallexample
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Perform a vector count leading zeros under bit mask operation, as if
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implemented by the Future @code{vclzdm} instruction.
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implemented by the @code{vclzdm} instruction.
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@findex vec_cntlzm
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@smallexample
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@ -20890,7 +20886,7 @@ implemented by the Future @code{vclzdm} instruction.
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@exdent vec_cnttzm (vector unsigned long long int, vector unsigned long long int)
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@end smallexample
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Perform a vector count trailing zeros under bit mask operation, as if
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implemented by the Future @code{vctzdm} instruction.
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implemented by the @code{vctzdm} instruction.
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@findex vec_cnttzm
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@smallexample
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@ -20921,7 +20917,7 @@ value of @code{n} that is greater than 16 is treated as if it equaled 16.
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@exdent vector unsigned long long int
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@exdent vec_gnb (vector unsigned __int128, const unsigned char)
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@end smallexample
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Perform a 128-bit vector gather operation, as if implemented by the Future
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Perform a 128-bit vector gather operation, as if implemented by the
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@code{vgnb} instruction. The second argument must be a literal
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integer value between 2 and 7 inclusive.
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@findex vec_gnb
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@ -20939,10 +20935,10 @@ integer value between 2 and 7 inclusive.
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Extract a single element from the vector formed by catenating this function's
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first two arguments at the byte offset specified by this function's
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third argument. On big-endian targets, this function behaves as if
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implemented by the Future @code{vextdubvlx}, @code{vextduhvlx},
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implemented by the @code{vextdubvlx}, @code{vextduhvlx},
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@code{vextduwvlx}, or @code{vextddvlx} instructions, depending on the
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types of the function's first two arguments. On little-endian
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targets, this function behaves as if implemented by the Future
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targets, this function behaves as if implemented by the
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@code{vextdubvrx}, @code{vextduhvrx},
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@code{vextduwvrx}, or @code{vextddvrx} instructions.
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The byte offset of the element to be extracted is calculated
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@ -20966,12 +20962,12 @@ Extract a single element from the vector formed by catenating this function's
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first two arguments at the byte offset calculated by subtracting this
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function's third argument from 31. On big-endian targets, this
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function behaves as if
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implemented by the Future
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implemented by the
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@code{vextdubvrx}, @code{vextduhvrx},
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@code{vextduwvrx}, or @code{vextddvrx} instructions, depending on the
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types of the function's first two arguments.
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On little-endian
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targets, this function behaves as if implemented by the Future
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targets, this function behaves as if implemented by the
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@code{vextdubvlx}, @code{vextduhvlx},
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@code{vextduwvlx}, or @code{vextddvlx} instructions.
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The byte offset of the element to be extracted, measured from the
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@ -20987,7 +20983,7 @@ result is undefined.
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@exdent vec_pdep (vector unsigned long long int, vector unsigned long long int)
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@end smallexample
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Perform a vector parallel bits deposit operation, as if implemented by
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the Future @code{vpdepd} instruction.
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the @code{vpdepd} instruction.
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@findex vec_pdep
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@smallexample
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@ -20995,7 +20991,7 @@ the Future @code{vpdepd} instruction.
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@exdent vec_pext (vector unsigned long long int, vector unsigned long long int)
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@end smallexample
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Perform a vector parallel bit extract operation, as if implemented by
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the Future @code{vpextd} instruction.
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the @code{vpextd} instruction.
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@findex vec_pext
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@smallexample
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@ -21072,7 +21068,7 @@ zero element if the same argument is also passed to @code{vec_strir}.
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vector unsigned __int128, const unsigned int)
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@end smallexample
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Perform a 128-bit vector evaluate operation, as if implemented by the
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Future @code{xxeval} instruction. The fourth argument must be a literal
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@code{xxeval} instruction. The fourth argument must be a literal
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integer value between 0 and 255 inclusive.
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@findex vec_ternarylogic
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@ -21083,7 +21079,7 @@ integer value between 0 and 255 inclusive.
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@exdent vector unsigned int vec_genpcvm (vector unsigned long long int,
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const int)
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@end smallexample
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Generate PCV from specified Mask size, as if implemented by the Future
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Generate PCV from specified Mask size, as if implemented by the
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@code{xxgenpcvbm}, @code{xxgenpcvhm}, @code{xxgenpcvwm} instructions, where
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immediate value is either 0, 1, 2 or 3.
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@findex vec_genpcvm
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