[AArch64 Testsuite] Fix fallout from FCM changes.
gcc/testsuite/ * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. (test_vceqd_s64): Force arguments to SIMD registers. (test_vceqzd_s64): Likewise. (test_vcged_s64): Likewise. (test_vcled_s64): Likewise. (test_vcgezd_s64): Likewise. (test_vcged_u64): Likewise. (test_vcgtd_s64): Likewise. (test_vcltd_s64): Likewise. (test_vcgtzd_s64): Likewise. (test_vcgtd_u64): Likewise. (test_vclezd_s64): Likewise. (test_vcltzd_s64): Likewise. (test_vtst_s64): Likewise. (test_vtst_u64): Likewise. From-SVN: r198493
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James Greenhalgh
James Greenhalgh
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@ -1,3 +1,21 @@
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2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/scalar_intrinsics.c (force_simd): New.
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(test_vceqd_s64): Force arguments to SIMD registers.
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(test_vceqzd_s64): Likewise.
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(test_vcged_s64): Likewise.
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(test_vcled_s64): Likewise.
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(test_vcgezd_s64): Likewise.
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(test_vcged_u64): Likewise.
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(test_vcgtd_s64): Likewise.
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(test_vcltd_s64): Likewise.
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(test_vcgtzd_s64): Likewise.
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(test_vcgtd_u64): Likewise.
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(test_vclezd_s64): Likewise.
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(test_vcltzd_s64): Likewise.
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(test_vtst_s64): Likewise.
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(test_vtst_u64): Likewise.
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2013-05-01 Paolo Carlini <paolo.carlini@oracle.com>
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PR c++/57092
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@ -1,7 +1,13 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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#include "../../../config/aarch64/arm_neon.h"
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#include <arm_neon.h>
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/* Used to force a variable to a SIMD register. */
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#define force_simd(V1) asm volatile ("mov %d0, %d1" \
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: "=w"(V1) \
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: "w"(V1) \
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: /* No clobbers */);
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/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */
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@ -31,7 +37,12 @@ test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
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uint64x1_t
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test_vceqd_s64 (int64x1_t a, int64x1_t b)
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{
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return vceqd_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vceqd_s64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
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@ -39,7 +50,11 @@ test_vceqd_s64 (int64x1_t a, int64x1_t b)
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uint64x1_t
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test_vceqzd_s64 (int64x1_t a)
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{
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return vceqzd_s64 (a);
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uint64x1_t res;
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force_simd (a);
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res = vceqzd_s64 (a);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
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@ -47,21 +62,36 @@ test_vceqzd_s64 (int64x1_t a)
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uint64x1_t
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test_vcged_s64 (int64x1_t a, int64x1_t b)
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{
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return vcged_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcged_s64 (a, b);
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force_simd (res);
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return res;
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}
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uint64x1_t
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test_vcled_s64 (int64x1_t a, int64x1_t b)
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{
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return vcled_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcled_s64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
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/* Idiom recognition will cause this testcase not to generate
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the expected cmge instruction, so do not check for it. */
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uint64x1_t
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test_vcgezd_s64 (int64x1_t a)
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{
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return vcgezd_s64 (a);
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uint64x1_t res;
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force_simd (a);
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res = vcgezd_s64 (a);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
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@ -69,7 +99,12 @@ test_vcgezd_s64 (int64x1_t a)
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uint64x1_t
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test_vcged_u64 (uint64x1_t a, uint64x1_t b)
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{
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return vcged_u64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcged_u64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
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@ -77,13 +112,23 @@ test_vcged_u64 (uint64x1_t a, uint64x1_t b)
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uint64x1_t
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test_vcgtd_s64 (int64x1_t a, int64x1_t b)
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{
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return vcgtd_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcgtd_s64 (a, b);
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force_simd (res);
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return res;
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}
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uint64x1_t
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test_vcltd_s64 (int64x1_t a, int64x1_t b)
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{
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return vcltd_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcltd_s64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
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@ -91,7 +136,11 @@ test_vcltd_s64 (int64x1_t a, int64x1_t b)
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uint64x1_t
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test_vcgtzd_s64 (int64x1_t a)
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{
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return vcgtzd_s64 (a);
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uint64x1_t res;
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force_simd (a);
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res = vcgtzd_s64 (a);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
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@ -99,7 +148,12 @@ test_vcgtzd_s64 (int64x1_t a)
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uint64x1_t
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test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
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{
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return vcgtd_u64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vcgtd_u64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
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@ -107,15 +161,24 @@ test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
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uint64x1_t
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test_vclezd_s64 (int64x1_t a)
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{
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return vclezd_s64 (a);
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uint64x1_t res;
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force_simd (a);
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res = vclezd_s64 (a);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
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/* Idiom recognition will cause this testcase not to generate
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the expected cmlt instruction, so do not check for it. */
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uint64x1_t
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test_vcltzd_s64 (int64x1_t a)
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{
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return vcltzd_s64 (a);
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uint64x1_t res;
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force_simd (a);
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res = vcltzd_s64 (a);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */
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@ -179,13 +242,23 @@ test_vdupd_lane_u64 (uint64x2_t a)
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int64x1_t
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test_vtst_s64 (int64x1_t a, int64x1_t b)
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{
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return vtstd_s64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vtstd_s64 (a, b);
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force_simd (res);
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return res;
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}
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uint64x1_t
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test_vtst_u64 (uint64x1_t a, uint64x1_t b)
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{
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return vtstd_u64 (a, b);
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uint64x1_t res;
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force_simd (a);
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force_simd (b);
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res = vtstd_s64 (a, b);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
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@ -722,7 +795,10 @@ test_vrshld_u64 (uint64x1_t a, uint64x1_t b)
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return vrshld_u64 (a, b);
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}
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/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */
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/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),
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so we cannot check scan-assembler-times. */
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/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */
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int64x1_t
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test_vshrd_n_s64 (int64x1_t a)
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