S/390: arch13: vector shift double by bit builtins
gcc/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390-builtin-types.def: Add new builtin function
types.
* config/s390/s390-builtins.def (s390_vec_sldb, s390_vec_srdb):
New overloaded builtins.
(s390_vec_sldb, s390_vec_srdb): New low-level builtins. and
s390_vsrd.
* config/s390/s390.md (UNSPEC_VEC_SLDB): Rename to ...
(UNSPEC_VEC_SLDBYTE): ... this.
(UNSPEC_VEC_SLDBIT, UNSPEC_VEC_SRDBIT): New constant definitions.
* config/s390/vecintrin.h (vec_sldb, vec_srdb): New builtin name
definitions.
* config/s390/vx-builtins.md ("vec_sld<mode>", "vec_sldw<mode>"):
Rename UNSPEC_VEC_SLDB to UNSPEC_VEC_SLDBYTE.
("vec_sldb<mode>", "vec_srdb<mode>"): New insn definitions.
gcc/testsuite/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c: New test.
* gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c: New test.
From-SVN: r270089
This commit is contained in:
Andreas Krebbel
Andreas Krebbel
parent
6913111a95
commit
ad7a3e3997
@ -1,3 +1,20 @@
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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* config/s390/s390-builtin-types.def: Add new builtin function
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types.
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* config/s390/s390-builtins.def (s390_vec_sldb, s390_vec_srdb):
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New overloaded builtins.
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(s390_vec_sldb, s390_vec_srdb): New low-level builtins. and
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s390_vsrd.
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* config/s390/s390.md (UNSPEC_VEC_SLDB): Rename to ...
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(UNSPEC_VEC_SLDBYTE): ... this.
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(UNSPEC_VEC_SLDBIT, UNSPEC_VEC_SRDBIT): New constant definitions.
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* config/s390/vecintrin.h (vec_sldb, vec_srdb): New builtin name
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definitions.
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* config/s390/vx-builtins.md ("vec_sld<mode>", "vec_sldw<mode>"):
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Rename UNSPEC_VEC_SLDB to UNSPEC_VEC_SLDBYTE.
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("vec_sldb<mode>", "vec_srdb<mode>"): New insn definitions.
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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("*vec_splats_bswap_vec<mode>", "*vec_splats_bswap_elem<mode>"):
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@ -285,6 +285,7 @@ DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT
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DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR)
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DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI)
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DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UCHAR)
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DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UINT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UINT)
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DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_ULONGLONG)
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DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, BT_UV16QI, BT_UCHAR, BT_INT)
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DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT)
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@ -513,6 +514,7 @@ DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI,
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UINT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UINT)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR)
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@ -544,6 +546,7 @@ DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_BV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_BV2DI)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UINT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UINT)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV16QI)
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@ -581,6 +584,7 @@ DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_BV4
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINT)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV16QI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV16QI)
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@ -621,6 +625,7 @@ DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_BV8
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UINT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UINT)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV16QI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI)
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@ -651,6 +656,7 @@ DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_BV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_BV16QI)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INT, BT_V16QI, BT_V16QI, BT_V16QI, BT_INT)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UINT, BT_V16QI, BT_V16QI, BT_V16QI, BT_UINT)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_ULONGLONG, BT_V16QI, BT_V16QI, BT_V16QI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI)
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@ -675,6 +681,7 @@ DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR, BT_V2DF, BT_V2DF, BT_UV2DI
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_BV2DI)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UINT, BT_V2DF, BT_V2DF, BT_V2DF, BT_UINT)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_ULONGLONG, BT_V2DF, BT_V2DF, BT_V2DF, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI)
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@ -705,6 +712,7 @@ DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV8HI, BT_V2DI, BT_V2DI, BT_UV8HI)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_BV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_BV2DI)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_INT, BT_V2DI, BT_V2DI, BT_V2DI, BT_INT)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UINT, BT_V2DI, BT_V2DI, BT_V2DI, BT_UINT)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_ULONGLONG, BT_V2DI, BT_V2DI, BT_V2DI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV16QI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV2DI)
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@ -728,6 +736,7 @@ DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_UV4SI)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI_FLTCONSTPTR_UCHAR, BT_V4SF, BT_V4SF, BT_UV4SI, BT_FLTCONSTPTR, BT_UCHAR)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_BV4SI)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UINT, BT_V4SF, BT_V4SF, BT_V4SF, BT_UINT)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_ULONGLONG, BT_V4SF, BT_V4SF, BT_V4SF, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV16QI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV4SI)
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@ -759,6 +768,7 @@ DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_BV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_BV4SI)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INT, BT_V4SI, BT_V4SI, BT_V4SI, BT_INT)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UINT, BT_V4SI, BT_V4SI, BT_V4SI, BT_UINT)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_ULONGLONG, BT_V4SI, BT_V4SI, BT_V4SI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV16QI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV4SI)
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@ -794,6 +804,7 @@ DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_BV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_BV8HI)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INT, BT_V8HI, BT_V8HI, BT_V8HI, BT_INT)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_V8HI, BT_INTPTR)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UINT, BT_V8HI, BT_V8HI, BT_V8HI, BT_UINT)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_ULONGLONG, BT_V8HI, BT_V8HI, BT_V8HI, BT_ULONGLONG)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV16QI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV16QI)
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DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV8HI)
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@ -2923,3 +2923,31 @@ B_DEF (s390_vsterf, eltswapv4si, 0,
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B_DEF (s390_vsterg, eltswapv2di, 0, B_VX, 0, BT_FN_V2DI_V2DI)
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B_DEF (s390_vsterf_flt, eltswapv4sf, 0, B_VXE, 0, BT_FN_V4SF_V4SF)
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B_DEF (s390_vsterg_dbl, eltswapv2df, 0, B_VX, 0, BT_FN_V2DF_V2DF)
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OB_DEF (s390_vec_sldb, s390_vec_sldb_s8, s390_vec_sldb_dbl, B_VXE2, BT_FN_OV4SI_OV4SI_OV4SI_UINT)
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OB_DEF_VAR (s390_vec_sldb_s8, s390_vsld, 0, O3_U3, BT_OV_V16QI_V16QI_V16QI_UINT)
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OB_DEF_VAR (s390_vec_sldb_u8, s390_vsld, 0, O3_U3, BT_OV_UV16QI_UV16QI_UV16QI_UINT)
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OB_DEF_VAR (s390_vec_sldb_s16, s390_vsld, 0, O3_U3, BT_OV_V8HI_V8HI_V8HI_UINT)
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OB_DEF_VAR (s390_vec_sldb_u16, s390_vsld, 0, O3_U3, BT_OV_UV8HI_UV8HI_UV8HI_UINT)
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OB_DEF_VAR (s390_vec_sldb_s32, s390_vsld, 0, O3_U3, BT_OV_V4SI_V4SI_V4SI_UINT)
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OB_DEF_VAR (s390_vec_sldb_u32, s390_vsld, 0, O3_U3, BT_OV_UV4SI_UV4SI_UV4SI_UINT)
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OB_DEF_VAR (s390_vec_sldb_s64, s390_vsld, 0, O3_U3, BT_OV_V2DI_V2DI_V2DI_UINT)
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OB_DEF_VAR (s390_vec_sldb_u64, s390_vsld, 0, O3_U3, BT_OV_UV2DI_UV2DI_UV2DI_UINT)
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OB_DEF_VAR (s390_vec_sldb_flt, s390_vsld, 0, O3_U3, BT_OV_V4SF_V4SF_V4SF_UINT)
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OB_DEF_VAR (s390_vec_sldb_dbl, s390_vsld, 0, O3_U3, BT_OV_V2DF_V2DF_V2DF_UINT)
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B_DEF (s390_vsld, vec_sldbv16qi, 0, B_VXE2, O3_U3, BT_FN_UV16QI_UV16QI_UV16QI_INT)
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OB_DEF (s390_vec_srdb, s390_vec_srdb_s8, s390_vec_srdb_dbl, B_VXE2, BT_FN_OV4SI_OV4SI_OV4SI_UINT)
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OB_DEF_VAR (s390_vec_srdb_s8, s390_vsrd, 0, O3_U3, BT_OV_V16QI_V16QI_V16QI_UINT)
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OB_DEF_VAR (s390_vec_srdb_u8, s390_vsrd, 0, O3_U3, BT_OV_UV16QI_UV16QI_UV16QI_UINT)
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OB_DEF_VAR (s390_vec_srdb_s16, s390_vsrd, 0, O3_U3, BT_OV_V8HI_V8HI_V8HI_UINT)
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OB_DEF_VAR (s390_vec_srdb_u16, s390_vsrd, 0, O3_U3, BT_OV_UV8HI_UV8HI_UV8HI_UINT)
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OB_DEF_VAR (s390_vec_srdb_s32, s390_vsrd, 0, O3_U3, BT_OV_V4SI_V4SI_V4SI_UINT)
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OB_DEF_VAR (s390_vec_srdb_u32, s390_vsrd, 0, O3_U3, BT_OV_UV4SI_UV4SI_UV4SI_UINT)
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OB_DEF_VAR (s390_vec_srdb_s64, s390_vsrd, 0, O3_U3, BT_OV_V2DI_V2DI_V2DI_UINT)
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OB_DEF_VAR (s390_vec_srdb_u64, s390_vsrd, 0, O3_U3, BT_OV_UV2DI_UV2DI_UV2DI_UINT)
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OB_DEF_VAR (s390_vec_srdb_flt, s390_vsrd, 0, O3_U3, BT_OV_V4SF_V4SF_V4SF_UINT)
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OB_DEF_VAR (s390_vec_srdb_dbl, s390_vsrd, 0, O3_U3, BT_OV_V2DF_V2DF_V2DF_UINT)
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B_DEF (s390_vsrd, vec_srdbv16qi, 0, B_VXE2, O3_U3, BT_FN_UV16QI_UV16QI_UV16QI_INT)
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@ -194,7 +194,9 @@
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UNSPEC_VEC_RL_MASK
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UNSPEC_VEC_SLL
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UNSPEC_VEC_SLB
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UNSPEC_VEC_SLDB
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UNSPEC_VEC_SLDBYTE
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UNSPEC_VEC_SLDBIT
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UNSPEC_VEC_SRDBIT
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UNSPEC_VEC_SRAL
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UNSPEC_VEC_SRAB
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UNSPEC_VEC_SRL
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@ -327,4 +327,6 @@ __lcbb(const void *ptr, int bndry)
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#define vec_fp_test_data_class __builtin_s390_vec_fp_test_data_class
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#define vec_revb __builtin_s390_vec_revb
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#define vec_reve __builtin_s390_vec_reve
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#define vec_sldb __builtin_s390_vec_sldb
|
||||
#define vec_srdb __builtin_s390_vec_srdb
|
||||
#endif /* _VECINTRIN_H */
|
||||
|
||||
@ -1030,7 +1030,7 @@
|
||||
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
|
||||
(match_operand:V_HW 2 "register_operand" "v")
|
||||
(match_operand:QI 3 "const_int_operand" "C")]
|
||||
UNSPEC_VEC_SLDB))]
|
||||
UNSPEC_VEC_SLDBYTE))]
|
||||
"TARGET_VX"
|
||||
"vsldb\t%v0,%v1,%v2,%b3"
|
||||
[(set_attr "op_type" "VRI")])
|
||||
@ -1040,12 +1040,36 @@
|
||||
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
|
||||
(match_operand:V_HW 2 "register_operand" "")
|
||||
(match_operand:QI 3 "const_int_operand" "")]
|
||||
UNSPEC_VEC_SLDB))]
|
||||
UNSPEC_VEC_SLDBYTE))]
|
||||
"TARGET_VX"
|
||||
{
|
||||
operands[3] = GEN_INT (INTVAL (operands[3]) << 2);
|
||||
})
|
||||
|
||||
; Vector shift left double by bit
|
||||
|
||||
(define_insn "vec_sldb<mode>"
|
||||
[(set (match_operand:V_HW 0 "register_operand" "=v")
|
||||
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
|
||||
(match_operand:V_HW 2 "register_operand" "v")
|
||||
(match_operand:QI 3 "const_int_operand" "C")]
|
||||
UNSPEC_VEC_SLDBIT))]
|
||||
"TARGET_VXE2"
|
||||
"vsld\t%v0,%v1,%v2,%b3"
|
||||
[(set_attr "op_type" "VRI")])
|
||||
|
||||
; Vector shift right double by bit
|
||||
|
||||
(define_insn "vec_srdb<mode>"
|
||||
[(set (match_operand:V_HW 0 "register_operand" "=v")
|
||||
(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
|
||||
(match_operand:V_HW 2 "register_operand" "v")
|
||||
(match_operand:QI 3 "const_int_operand" "C")]
|
||||
UNSPEC_VEC_SRDBIT))]
|
||||
"TARGET_VXE2"
|
||||
"vsrd\t%v0,%v1,%v2,%b3"
|
||||
[(set_attr "op_type" "VRI")])
|
||||
|
||||
; Vector shift right arithmetic
|
||||
|
||||
(define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
|
||||
|
||||
* gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c: New test.
|
||||
* gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c: New test.
|
||||
|
||||
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
|
||||
|
||||
* gcc.target/s390/zvector/replicate-bswap-1.c: New test.
|
||||
|
||||
@ -0,0 +1,69 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
|
||||
|
||||
#include <vecintrin.h>
|
||||
|
||||
vector unsigned char
|
||||
foo1 (vector unsigned char a, vector unsigned char b)
|
||||
{
|
||||
return vec_sldb (a, b, 0);
|
||||
}
|
||||
|
||||
vector signed char
|
||||
foo2 (vector signed char a, vector signed char b)
|
||||
{
|
||||
return vec_sldb (a, b, 1);
|
||||
}
|
||||
|
||||
|
||||
vector unsigned short
|
||||
foo3 (vector unsigned short a, vector unsigned short b)
|
||||
{
|
||||
return vec_sldb (a, b, 2);
|
||||
}
|
||||
|
||||
vector signed short
|
||||
foo4 (vector signed short a, vector signed short b)
|
||||
{
|
||||
return vec_sldb (a, b, 3);
|
||||
}
|
||||
|
||||
vector unsigned int
|
||||
foo5 (vector unsigned int a, vector unsigned int *b)
|
||||
{
|
||||
return vec_sldb (a, *b, 4);
|
||||
}
|
||||
|
||||
vector signed int
|
||||
foo6 (vector signed int a, vector signed int b)
|
||||
{
|
||||
return vec_sldb (a, b, 5);
|
||||
}
|
||||
|
||||
|
||||
vector unsigned long long
|
||||
foo7 (vector unsigned long long a, vector unsigned long long b)
|
||||
{
|
||||
return vec_sldb (a, (vector unsigned long long){ 1, 2 }, 6);
|
||||
}
|
||||
|
||||
vector signed long long
|
||||
foo8 (vector signed long long a, vector signed long long b)
|
||||
{
|
||||
return vec_sldb (a, b, 7);
|
||||
}
|
||||
|
||||
|
||||
vector float
|
||||
foo9 (vector float a, vector float b)
|
||||
{
|
||||
return vec_sldb (a, b, 1);
|
||||
}
|
||||
|
||||
vector double
|
||||
foo10 (vector double a, vector double b)
|
||||
{
|
||||
return vec_sldb (a, b, 3);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "vsld" 10 } } */
|
||||
@ -0,0 +1,69 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
|
||||
|
||||
#include <vecintrin.h>
|
||||
|
||||
vector unsigned char
|
||||
foo1 (vector unsigned char a, vector unsigned char b)
|
||||
{
|
||||
return vec_srdb (a, b, 0);
|
||||
}
|
||||
|
||||
vector signed char
|
||||
foo2 (vector signed char a, vector signed char b)
|
||||
{
|
||||
return vec_srdb (a, b, 1);
|
||||
}
|
||||
|
||||
|
||||
vector unsigned short
|
||||
foo3 (vector unsigned short a, vector unsigned short b)
|
||||
{
|
||||
return vec_srdb (a, b, 2);
|
||||
}
|
||||
|
||||
vector signed short
|
||||
foo4 (vector signed short a, vector signed short b)
|
||||
{
|
||||
return vec_srdb (a, b, 3);
|
||||
}
|
||||
|
||||
vector unsigned int
|
||||
foo5 (vector unsigned int a, vector unsigned int *b)
|
||||
{
|
||||
return vec_srdb (a, *b, 4);
|
||||
}
|
||||
|
||||
vector signed int
|
||||
foo6 (vector signed int a, vector signed int b)
|
||||
{
|
||||
return vec_srdb (a, b, 5);
|
||||
}
|
||||
|
||||
|
||||
vector unsigned long long
|
||||
foo7 (vector unsigned long long a, vector unsigned long long b)
|
||||
{
|
||||
return vec_srdb (a, (vector unsigned long long){ 1, 2 }, 6);
|
||||
}
|
||||
|
||||
vector signed long long
|
||||
foo8 (vector signed long long a, vector signed long long b)
|
||||
{
|
||||
return vec_srdb (a, b, 7);
|
||||
}
|
||||
|
||||
|
||||
vector float
|
||||
foo9 (vector float a, vector float b)
|
||||
{
|
||||
return vec_srdb (a, b, 1);
|
||||
}
|
||||
|
||||
vector double
|
||||
foo10 (vector double a, vector double b)
|
||||
{
|
||||
return vec_srdb (a, b, 3);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "vsrd" 10 } } */
|
||||
Loading…
Reference in New Issue
Block a user