re PR target/46091 (missed optimization: x86 bt/btc/bts instructions)
PR target/46091 * config/i386/i386.md (*anddi_1_btr): Change predicates of operand 0 and operand 1 to nomimmediate_operand. Add "m" constraint. Add ix86_binary_operator_ok to insn constraint. (*iordi_1_bts): Ditto. (*xordi_1_btc): Ditto. (*btsq): Change predicate of operand 0 to nonimmediate_operand. Update corresponding peephole2 pattern. (*btrq): Ditto. (*btcq): Ditto. testsuite/ChangeLog: PR target/46091 * gcc.target/i386/pr46091-1.c: Update scan-assembler-times. (testm): New test function. * gcc.target/i386/pr46091-2.c: Ditto. * gcc.target/i386/pr46091-3.c: Ditto. From-SVN: r251124
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Uros Bizjak
Uros Bizjak
parent
90d43c80aa
commit
adb5b54b28
@ -1,3 +1,16 @@
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2017-08-16 Uros Bizjak <ubizjak@gmail.com>
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PR target/46091
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* config/i386/i386.md (*anddi_1_btr): Change predicates of
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operand 0 and operand 1 to nomimmediate_operand. Add "m" constraint.
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Add ix86_binary_operator_ok to insn constraint.
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(*iordi_1_bts): Ditto.
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(*xordi_1_btc): Ditto.
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(*btsq): Change predicate of operand 0 to nonimmediate_operand.
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Update corresponding peephole2 pattern.
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(*btrq): Ditto.
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(*btcq): Ditto.
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2017-08-16 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/81832
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@ -8268,12 +8268,13 @@
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(set_attr "mode" "SI,DI,DI,SI")])
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(define_insn_and_split "*anddi_1_btr"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(and:DI
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(match_operand:DI 1 "register_operand" "%0")
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(match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "const_int_operand" "n")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && TARGET_USE_BT
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&& ix86_binary_operator_ok (AND, DImode, operands)
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&& IN_RANGE (exact_log2 (~INTVAL (operands[2])), 31, 63)"
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"#"
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"&& reload_completed"
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@ -8813,12 +8814,13 @@
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*iordi_1_bts"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(ior:DI
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(match_operand:DI 1 "register_operand" "%0")
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(match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "const_int_operand" "n")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && TARGET_USE_BT
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&& ix86_binary_operator_ok (IOR, DImode, operands)
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&& IN_RANGE (exact_log2 (INTVAL (operands[2])), 31, 63)"
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"#"
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"&& reload_completed"
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@ -8834,12 +8836,13 @@
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(set_attr "mode" "DI")])
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(define_insn_and_split "*xordi_1_btc"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(xor:DI
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(match_operand:DI 1 "register_operand" "%0")
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(match_operand:DI 1 "nonimmediate_operand" "%0")
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(match_operand:DI 2 "const_int_operand" "n")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && TARGET_USE_BT
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&& ix86_binary_operator_ok (XOR, DImode, operands)
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&& IN_RANGE (exact_log2 (INTVAL (operands[2])), 31, 63)"
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"#"
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"&& reload_completed"
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@ -10996,10 +10999,10 @@
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;; Bit set / bit test instructions
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;; %%% bts, btr, btc, bt.
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;; In general these instructions are *slow* when applied to memory,
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;; since they enforce atomic operation. When applied to registers,
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;; it depends on the cpu implementation. They're never faster than
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;; the corresponding and/ior/xor operations, so with 32-bit there's
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;; In general these instructions are *slow* with variable operand
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;; when applied to memory. When applied to registers, it depends
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;; on the cpu implementation. They're never faster than the
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;; corresponding and/ior/xor operations, so with 32-bit there's
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;; no point. But in 64-bit, we can't hold the relevant immediates
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;; within the instruction itself, so operating on bits in the high
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;; 32-bits of a register becomes easier.
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@ -11009,7 +11012,7 @@
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;; negdf respectively, so they can never be disabled entirely.
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(define_insn "*btsq"
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[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand" "J"))
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(const_int 1))
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@ -11022,7 +11025,7 @@
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(set_attr "mode" "DI")])
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(define_insn "*btrq"
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[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand" "J"))
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(const_int 0))
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@ -11035,7 +11038,7 @@
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(set_attr "mode" "DI")])
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(define_insn "*btcq"
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[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
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[(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand" "J"))
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(not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
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@ -11052,7 +11055,7 @@
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(define_peephole2
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[(match_scratch:DI 2 "r")
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "register_operand")
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(const_int 1))
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@ -11076,7 +11079,7 @@
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(define_peephole2
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[(match_scratch:DI 2 "r")
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "register_operand")
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(const_int 0))
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@ -11100,7 +11103,7 @@
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(define_peephole2
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[(match_scratch:DI 2 "r")
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(parallel [(set (zero_extract:DI
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(match_operand:DI 0 "register_operand")
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(match_operand:DI 0 "nonimmediate_operand")
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(const_int 1)
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(match_operand 1 "const_0_to_63_operand"))
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(not:DI (zero_extract:DI
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@ -11128,7 +11131,7 @@
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(zero_extract:SWI48
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(match_operand:SWI48 0 "register_operand" "r")
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(const_int 1)
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(match_operand:SI 1 "nonmemory_operand" "rN"))
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(match_operand:SI 1 "nonmemory_operand" "r<S>"))
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(const_int 0)))]
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""
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{
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@ -1,3 +1,11 @@
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2017-08-16 Uros Bizjak <ubizjak@gmail.com>
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PR target/46091
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* gcc.target/i386/pr46091-1.c: Update scan-assembler-times.
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(testm): New test function.
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* gcc.target/i386/pr46091-2.c: Ditto.
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* gcc.target/i386/pr46091-3.c: Ditto.
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2017-08-16 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/81832
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@ -6,4 +6,11 @@ unsigned long long test (unsigned long long a)
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return a & ~(1ull << 55);
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}
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/* { dg-final { scan-assembler "btr" } } */
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extern unsigned long long m;
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void testm (void)
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{
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m &= ~(1ull << 45);
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}
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/* { dg-final { scan-assembler-times "btr" 2 } } */
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@ -6,4 +6,11 @@ unsigned long long test (unsigned long long a)
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return a | (1ull << 55);
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}
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/* { dg-final { scan-assembler "bts" } } */
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extern unsigned long long m;
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void testm (void)
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{
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m |= (1ull << 45);
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}
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/* { dg-final { scan-assembler-times "bts" 2 } } */
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@ -6,4 +6,11 @@ unsigned long long test (unsigned long long a)
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return a ^ (1ull << 55);
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}
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/* { dg-final { scan-assembler "btc" } } */
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extern unsigned long long m;
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void testm (void)
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{
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m ^= (1ull << 45);
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}
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/* { dg-final { scan-assembler-times "btc" 2 } } */
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