re PR middle-end/55030 (gcc.c-torture/execute/builtins/memcpy-chk.c execution, -Os (et al))
PR middle-end/55030 * builtins.c (expand_builtin_setjmp_receiver): Update comment regarding purpose of blockage. * emit-rtl.c [!HAVE_blockage] (gen_blockage): Similarly for the head comment. * rtlanal.c (volatile_insn_p): Ditto. * doc/md.texi (blockage): Update similarly. Change wording to require one of two forms, rather than implying a wider choice. * cse.c (cse_insn): Where checking for blocking insns, use volatile_insn_p instead of manual check for volatile ASM. * dse.c (scan_insn): Ditto. * cselib.c (cselib_process_insn): Ditto. From-SVN: r193802
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@ -1,3 +1,18 @@
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2012-11-26 Hans-Peter Nilsson <hp@bitrange.com>
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PR middle-end/55030
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* builtins.c (expand_builtin_setjmp_receiver): Update comment
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regarding purpose of blockage.
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* emit-rtl.c [!HAVE_blockage] (gen_blockage): Similarly for
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the head comment.
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* rtlanal.c (volatile_insn_p): Ditto.
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* doc/md.texi (blockage): Update similarly. Change wording to
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require one of two forms, rather than implying a wider choice.
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* cse.c (cse_insn): Where checking for blocking insns, use
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volatile_insn_p instead of manual check for volatile ASM.
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* dse.c (scan_insn): Ditto.
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* cselib.c (cselib_process_insn): Ditto.
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2012-11-25 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (<sse>_loadu<ssemodesuffix><avxsizesuffix>):
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@ -951,7 +951,8 @@ expand_builtin_setjmp_receiver (rtx receiver_label ATTRIBUTE_UNUSED)
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/* We must not allow the code we just generated to be reordered by
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scheduling. Specifically, the update of the frame pointer must
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happen immediately, not later. */
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happen immediately, not later. Similarly, we must block
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(frame-related) register values to be used across this code. */
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emit_insn (gen_blockage ());
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}
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@ -5661,10 +5661,9 @@ cse_insn (rtx insn)
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invalidate (XEXP (dest, 0), GET_MODE (dest));
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}
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/* A volatile ASM invalidates everything. */
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/* A volatile ASM or an UNSPEC_VOLATILE invalidates everything. */
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if (NONJUMP_INSN_P (insn)
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&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
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&& MEM_VOLATILE_P (PATTERN (insn)))
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&& volatile_insn_p (PATTERN (insn)))
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flush_hash_table ();
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/* Don't cse over a call to setjmp; on some machines (eg VAX)
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@ -2625,13 +2625,12 @@ cselib_process_insn (rtx insn)
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cselib_current_insn = insn;
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/* Forget everything at a CODE_LABEL, a volatile asm, or a setjmp. */
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/* Forget everything at a CODE_LABEL, a volatile insn, or a setjmp. */
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if (LABEL_P (insn)
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|| (CALL_P (insn)
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&& find_reg_note (insn, REG_SETJMP, NULL))
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|| (NONJUMP_INSN_P (insn)
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&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
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&& MEM_VOLATILE_P (PATTERN (insn))))
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&& volatile_insn_p (PATTERN (insn))))
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{
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cselib_reset_table (next_uid);
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cselib_current_insn = NULL_RTX;
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@ -5972,8 +5972,9 @@ the values of operands 1 and 2.
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@item @samp{blockage}
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This pattern defines a pseudo insn that prevents the instruction
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scheduler from moving instructions across the boundary defined by the
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blockage insn. Normally an UNSPEC_VOLATILE pattern.
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scheduler and other passes from moving instructions and using register
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equivalences across the boundary defined by the blockage insn.
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This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
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@cindex @code{memory_barrier} instruction pattern
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@item @samp{memory_barrier}
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@ -2522,8 +2522,7 @@ scan_insn (bb_info_t bb_info, rtx insn)
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/* Cselib clears the table for this case, so we have to essentially
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do the same. */
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if (NONJUMP_INSN_P (insn)
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&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
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&& MEM_VOLATILE_P (PATTERN (insn)))
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&& volatile_insn_p (PATTERN (insn)))
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{
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add_wild_read (bb_info);
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insn_info->cannot_delete = true;
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@ -363,8 +363,8 @@ get_reg_attrs (tree decl, int offset)
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#if !HAVE_blockage
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/* Generate an empty ASM_INPUT, which is used to block attempts to schedule
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across this insn. */
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/* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
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and to block register equivalences to be seen across this insn. */
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rtx
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gen_blockage (void)
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@ -2082,8 +2082,8 @@ remove_node_from_expr_list (const_rtx node, rtx *listp)
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/* Nonzero if X contains any volatile instructions. These are instructions
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which may cause unpredictable machine state instructions, and thus no
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instructions should be moved or combined across them. This includes
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only volatile asms and UNSPEC_VOLATILE instructions. */
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instructions or register uses should be moved or combined across them.
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This includes only volatile asms and UNSPEC_VOLATILE instructions. */
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int
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volatile_insn_p (const_rtx x)
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