re PR middle-end/55030 (gcc.c-torture/execute/builtins/memcpy-chk.c execution, -Os (et al))

PR middle-end/55030
	* builtins.c (expand_builtin_setjmp_receiver): Update comment
	regarding purpose of blockage.
	* emit-rtl.c [!HAVE_blockage] (gen_blockage): Similarly for
	the head comment.
	* rtlanal.c (volatile_insn_p): Ditto.
	* doc/md.texi (blockage): Update similarly.  Change wording to
	require one of two forms, rather than implying a wider choice.
	* cse.c (cse_insn): Where checking for blocking insns, use
	volatile_insn_p instead of manual check for volatile ASM.
	* dse.c (scan_insn): Ditto.
	* cselib.c (cselib_process_insn): Ditto.

From-SVN: r193802
This commit is contained in:
Hans-Peter Nilsson 2012-11-26 03:22:15 +00:00 committed by Hans-Peter Nilsson
parent 15c115d38e
commit adddc3471f
8 changed files with 29 additions and 15 deletions

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@ -1,3 +1,18 @@
2012-11-26 Hans-Peter Nilsson <hp@bitrange.com>
PR middle-end/55030
* builtins.c (expand_builtin_setjmp_receiver): Update comment
regarding purpose of blockage.
* emit-rtl.c [!HAVE_blockage] (gen_blockage): Similarly for
the head comment.
* rtlanal.c (volatile_insn_p): Ditto.
* doc/md.texi (blockage): Update similarly. Change wording to
require one of two forms, rather than implying a wider choice.
* cse.c (cse_insn): Where checking for blocking insns, use
volatile_insn_p instead of manual check for volatile ASM.
* dse.c (scan_insn): Ditto.
* cselib.c (cselib_process_insn): Ditto.
2012-11-25 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (<sse>_loadu<ssemodesuffix><avxsizesuffix>):

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@ -951,7 +951,8 @@ expand_builtin_setjmp_receiver (rtx receiver_label ATTRIBUTE_UNUSED)
/* We must not allow the code we just generated to be reordered by
scheduling. Specifically, the update of the frame pointer must
happen immediately, not later. */
happen immediately, not later. Similarly, we must block
(frame-related) register values to be used across this code. */
emit_insn (gen_blockage ());
}

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@ -5661,10 +5661,9 @@ cse_insn (rtx insn)
invalidate (XEXP (dest, 0), GET_MODE (dest));
}
/* A volatile ASM invalidates everything. */
/* A volatile ASM or an UNSPEC_VOLATILE invalidates everything. */
if (NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
&& MEM_VOLATILE_P (PATTERN (insn)))
&& volatile_insn_p (PATTERN (insn)))
flush_hash_table ();
/* Don't cse over a call to setjmp; on some machines (eg VAX)

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@ -2625,13 +2625,12 @@ cselib_process_insn (rtx insn)
cselib_current_insn = insn;
/* Forget everything at a CODE_LABEL, a volatile asm, or a setjmp. */
/* Forget everything at a CODE_LABEL, a volatile insn, or a setjmp. */
if (LABEL_P (insn)
|| (CALL_P (insn)
&& find_reg_note (insn, REG_SETJMP, NULL))
|| (NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
&& MEM_VOLATILE_P (PATTERN (insn))))
&& volatile_insn_p (PATTERN (insn))))
{
cselib_reset_table (next_uid);
cselib_current_insn = NULL_RTX;

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@ -5972,8 +5972,9 @@ the values of operands 1 and 2.
@item @samp{blockage}
This pattern defines a pseudo insn that prevents the instruction
scheduler from moving instructions across the boundary defined by the
blockage insn. Normally an UNSPEC_VOLATILE pattern.
scheduler and other passes from moving instructions and using register
equivalences across the boundary defined by the blockage insn.
This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
@cindex @code{memory_barrier} instruction pattern
@item @samp{memory_barrier}

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@ -2522,8 +2522,7 @@ scan_insn (bb_info_t bb_info, rtx insn)
/* Cselib clears the table for this case, so we have to essentially
do the same. */
if (NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == ASM_OPERANDS
&& MEM_VOLATILE_P (PATTERN (insn)))
&& volatile_insn_p (PATTERN (insn)))
{
add_wild_read (bb_info);
insn_info->cannot_delete = true;

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@ -363,8 +363,8 @@ get_reg_attrs (tree decl, int offset)
#if !HAVE_blockage
/* Generate an empty ASM_INPUT, which is used to block attempts to schedule
across this insn. */
/* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
and to block register equivalences to be seen across this insn. */
rtx
gen_blockage (void)

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@ -2082,8 +2082,8 @@ remove_node_from_expr_list (const_rtx node, rtx *listp)
/* Nonzero if X contains any volatile instructions. These are instructions
which may cause unpredictable machine state instructions, and thus no
instructions should be moved or combined across them. This includes
only volatile asms and UNSPEC_VOLATILE instructions. */
instructions or register uses should be moved or combined across them.
This includes only volatile asms and UNSPEC_VOLATILE instructions. */
int
volatile_insn_p (const_rtx x)