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S/390: Get rid of Y constraint in left and logical right 

shift patterns.

With this patch the substitution patterns added earlier are used for
the logical right shift and all the left shift patterns.

2016-03-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md ("<shift><mode>3"): Change predicate of
	op2 to nonmemory_operand.
	("*<shift>di3_31", "*<shift>di3_31_and"):
	Merge into single pattern definition ...
	("*<shift>di3_31<addr_style_op><masked_op>"): New pattern.
	("*<shift><mode>3", "*<shift><mode>3_and"): Merge into single
	pattern definition ...
	("*<shift><mode>3<addr_style_op><masked_op>"): New pattern.
	* config/s390/subst.md: Add ashift and lshiftrt to SUBST
	iterator.

From-SVN: r233844
This commit is contained in:
Andreas Krebbel 2016-03-01 09:22:20 +00:00 committed by Andreas Krebbel
parent 191eb16d3a
commit adf22b3f5a
3 changed files with 30 additions and 40 deletions
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13
gcc/ChangeLog
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@ -1,3 +1,16 @@
2016-03-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.md ("<shift><mode>3"): Change predicate of
op2 to nonmemory_operand.
("*<shift>di3_31", "*<shift>di3_31_and"):
Merge into single pattern definition ...
("*<shift>di3_31<addr_style_op><masked_op>"): New pattern.
("*<shift><mode>3", "*<shift><mode>3_and"): Merge into single
pattern definition ...
("*<shift><mode>3<addr_style_op><masked_op>"): New pattern.
* config/s390/subst.md: Add ashift and lshiftrt to SUBST
iterator.
2016-03-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/predicates.md (const_int_6bitset_operand): New

55
gcc/config/s390/s390.md
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@ -8408,60 +8408,37 @@
(define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "")
(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
(match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
(match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
; ESA 64 bit register pair shift with reg or imm shift count
; sldl, srdl
(define_insn "*<shift>di3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
(define_insn "*<shift>di3_31<addr_style_op><masked_op>"
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "nonmemory_operand" "an")))]
"!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2"
"s<lr>dl\t%0,<addr_style_op_ops>"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")
(set_attr "z196prop" "z196_cracked")])
; 64 bit register shift with reg or imm shift count
; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
(define_insn "*<shift><mode>3<addr_style_op><masked_op>"
[(set (match_operand:GPR 0 "register_operand" "=d, d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
(match_operand:SI 2 "nonmemory_operand" "an,an")))]
""
"@
s<lr>l<g>\t%0,<1>%Y2
s<lr>l<gk>\t%0,%1,%Y2"
s<lr>l<g>\t%0,<1><addr_style_op_ops>
s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
[(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; sldl, srdl
(define_insn "*<shift>di3_31_and"
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))]
"!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3_and"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
(match_operand:SI 3 "const_int_operand" "n,n"))))]
"(INTVAL (operands[3]) & 63) == 63"
"@
s<lr>l<g>\t%0,<1>%Y2
s<lr>l<gk>\t%0,%1,%Y2"
[(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
(set_attr "z10prop" "z10_super_E1,*")])
;
; ashr(di|si)3 instruction pattern(s).

2
gcc/config/s390/subst.md
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@ -19,7 +19,7 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_code_iterator SUBST [rotate])
(define_code_iterator SUBST [rotate ashift lshiftrt])
; This expands an register/immediate operand to a register+immediate
; operand to draw advantage of the address style operand format