re PR target/11535 (__builtin_return_address may not work on ia64)
PR target/11535
* config/ia64/ia64.c (ia64_initial_elimination_offset): Remove
RETURN_ADDRESS_POINTER_REGNUM.
(ia64_expand_prologue): Don't frob it.
(ia64_output_function_epilogue): Likewise.
(ia64_return_addr_rtx): New.
(ia64_split_return_addr_rtx): New.
* config/ia64/ia64-protos.h: Update.
* config/ia64/ia64.h (FIRST_PSEUDO_REGISTER): Decrement.
(RETURN_ADDRESS_POINTER_REGNUM): Remove.
(GENERAL_REGNO_P): Don't check it.
(AR_*_REGNUM): Renumber.
(FIXED_REGISTERS): Remove RETURN_ADDRESS_POINTER_REGNUM.
(CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER, REG_CLASS_CONTENTS): Likewise.
(ELIMINABLE_REGS, REGISTER_NAMES): Likewise.
(RETURN_ADDR_RTX): Use ia64_return_addr_rtx.
* config/ia64/ia64.md (UNSPEC_RET_ADDR): New.
(movdi_ret_addr): New.
From-SVN: r70263
This commit is contained in:
Richard Henderson
Richard Henderson
parent
5dddb92059
commit
af1e551876
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@ -1,3 +1,25 @@
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2003-08-08 Richard Henderson <rth@redhat.com>
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PR target/11535
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* config/ia64/ia64.c (ia64_initial_elimination_offset): Remove
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RETURN_ADDRESS_POINTER_REGNUM.
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(ia64_expand_prologue): Don't frob it.
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(ia64_output_function_epilogue): Likewise.
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(ia64_return_addr_rtx): New.
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(ia64_split_return_addr_rtx): New.
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* config/ia64/ia64-protos.h: Update.
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* config/ia64/ia64.h (FIRST_PSEUDO_REGISTER): Decrement.
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(RETURN_ADDRESS_POINTER_REGNUM): Remove.
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(GENERAL_REGNO_P): Don't check it.
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(AR_*_REGNUM): Renumber.
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(FIXED_REGISTERS): Remove RETURN_ADDRESS_POINTER_REGNUM.
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(CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS): Likewise.
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(REG_ALLOC_ORDER, REG_CLASS_CONTENTS): Likewise.
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(ELIMINABLE_REGS, REGISTER_NAMES): Likewise.
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(RETURN_ADDR_RTX): Use ia64_return_addr_rtx.
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* config/ia64/ia64.md (UNSPEC_RET_ADDR): New.
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(movdi_ret_addr): New.
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2003-08-08 Geoffrey Keating <geoffk@apple.com>
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* config.gcc (powerpc-*-darwin*): Don't build a soft-float multilib.
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@ -139,6 +139,9 @@ extern void ia64_init_builtins PARAMS((void));
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extern void ia64_override_options PARAMS((void));
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extern int ia64_dbx_register_number PARAMS((int));
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extern rtx ia64_return_addr_rtx PARAMS ((HOST_WIDE_INT, rtx));
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extern void ia64_split_return_addr_rtx PARAMS ((rtx));
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#ifdef SDATA_SECTION_ASM_OP
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extern void sdata_section PARAMS ((void));
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#endif
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@ -2197,10 +2197,6 @@ ia64_initial_elimination_offset (from, to)
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abort ();
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break;
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case RETURN_ADDRESS_POINTER_REGNUM:
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offset = 0;
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break;
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default:
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abort ();
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}
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@ -2551,17 +2547,6 @@ ia64_expand_prologue ()
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reg_names[current_frame_info.reg_fp] = tmp;
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}
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/* Fix up the return address placeholder. */
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/* ??? We can fail if __builtin_return_address is used, and we didn't
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allocate a register in which to save b0. I can't think of a way to
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eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
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then be sure that I got the right one. Further, reload doesn't seem
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to care if an eliminable register isn't used, and "eliminates" it
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anyway. */
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if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
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&& current_frame_info.reg_save_b0 != 0)
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XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
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/* We don't need an alloc instruction if we've used no outputs or locals. */
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if (current_frame_info.n_local_regs == 0
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&& current_frame_info.n_output_regs == 0
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@ -3118,6 +3103,72 @@ ia64_direct_return ()
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return 0;
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}
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/* Return the magic cookie that we use to hold the return address
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during early compilation. */
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rtx
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ia64_return_addr_rtx (count, frame)
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HOST_WIDE_INT count;
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rtx frame ATTRIBUTE_UNUSED;
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{
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if (count != 0)
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return NULL;
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return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
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}
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/* Split this value after reload, now that we know where the return
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address is saved. */
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void
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ia64_split_return_addr_rtx (dest)
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rtx dest;
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{
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rtx src;
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if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
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{
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if (current_frame_info.reg_save_b0 != 0)
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src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
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else
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{
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HOST_WIDE_INT off;
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unsigned int regno;
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/* Compute offset from CFA for BR0. */
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/* ??? Must be kept in sync with ia64_expand_prologue. */
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off = (current_frame_info.spill_cfa_off
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+ current_frame_info.spill_size);
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for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
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if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
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off -= 8;
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/* Convert CFA offset to a register based offset. */
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if (frame_pointer_needed)
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src = hard_frame_pointer_rtx;
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else
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{
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src = stack_pointer_rtx;
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off += current_frame_info.total_size;
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}
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/* Load address into scratch register. */
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if (CONST_OK_FOR_I (off))
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emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
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else
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{
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emit_move_insn (dest, GEN_INT (off));
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emit_insn (gen_adddi3 (dest, src, dest));
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}
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src = gen_rtx_MEM (Pmode, dest);
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}
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}
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else
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src = gen_rtx_REG (DImode, BR_REG (0));
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emit_move_insn (dest, src);
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}
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int
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ia64_hard_regno_rename_ok (from, to)
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int from;
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@ -3267,9 +3318,6 @@ ia64_output_function_epilogue (file, size)
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{
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int i;
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/* Reset from the function's potential modifications. */
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XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
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if (current_frame_info.reg_fp)
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{
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const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
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@ -455,7 +455,7 @@ while (0)
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64 predicate registers, 8 branch registers, one frame pointer,
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and several "application" registers. */
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#define FIRST_PSEUDO_REGISTER 335
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#define FIRST_PSEUDO_REGISTER 334
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/* Ranges for the various kinds of registers. */
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#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
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@ -464,9 +464,7 @@ while (0)
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#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
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#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
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#define GENERAL_REGNO_P(REGNO) \
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(GR_REGNO_P (REGNO) \
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|| (REGNO) == FRAME_POINTER_REGNUM \
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|| (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
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(GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
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#define GR_REG(REGNO) ((REGNO) + 0)
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#define FR_REG(REGNO) ((REGNO) + 128)
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@ -476,11 +474,11 @@ while (0)
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#define IN_REG(REGNO) ((REGNO) + 112)
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#define LOC_REG(REGNO) ((REGNO) + 32)
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#define AR_CCV_REGNUM 330
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#define AR_UNAT_REGNUM 331
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#define AR_PFS_REGNUM 332
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#define AR_LC_REGNUM 333
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#define AR_EC_REGNUM 334
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#define AR_CCV_REGNUM 329
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#define AR_UNAT_REGNUM 330
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#define AR_PFS_REGNUM 331
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#define AR_LC_REGNUM 332
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#define AR_EC_REGNUM 333
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#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
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#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
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@ -543,8 +541,8 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Branch registers. */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/*FP RA CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 1, 0, 1 \
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/*FP CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 0, 1 \
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}
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/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
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@ -578,8 +576,8 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Branch registers. */ \
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1, 0, 0, 0, 0, 0, 1, 1, \
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/*FP RA CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 1, 0, 1 \
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/*FP CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 0, 1 \
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}
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/* Like `CALL_USED_REGISTERS' but used to overcome a historical
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@ -616,8 +614,8 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Branch registers. */ \
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1, 0, 0, 0, 0, 0, 1, 1, \
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/*FP RA CCV UNAT PFS LC EC */ \
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0, 0, 1, 0, 1, 0, 0 \
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/*FP CCV UNAT PFS LC EC */ \
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0, 1, 0, 1, 0, 0 \
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}
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@ -763,7 +761,7 @@ while (0)
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/* Special branch registers. */ \
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R_BR (0), \
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/* Other fixed registers. */ \
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FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
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FRAME_POINTER_REGNUM, \
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AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
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AR_EC_REGNUM \
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}
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@ -892,11 +890,11 @@ enum reg_class
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/* AR_M_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x0C00 }, \
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0x00000000, 0x00000000, 0x0600 }, \
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/* AR_I_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x7000 }, \
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0x00000000, 0x00000000, 0x3800 }, \
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/* ADDL_REGS. */ \
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{ 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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@ -904,7 +902,7 @@ enum reg_class
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/* GR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x0300 }, \
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0x00000000, 0x00000000, 0x0100 }, \
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/* FR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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@ -912,15 +910,15 @@ enum reg_class
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/* GR_AND_BR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x00000000, 0x00000000, \
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0x00000000, 0x00000000, 0x03FF }, \
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0x00000000, 0x00000000, 0x01FF }, \
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/* GR_AND_FR_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0x00000000, 0x00000000, 0x0300 }, \
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0x00000000, 0x00000000, 0x0100 }, \
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/* ALL_REGS. */ \
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
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0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
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0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
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}
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/* A C expression whose value is a register class containing hard register
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@ -1142,7 +1140,7 @@ enum reg_class
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DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
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#define RETURN_ADDR_RTX(COUNT, FRAME) \
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((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
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ia64_return_addr_rtx (COUNT, FRAME)
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/* A C expression whose value is RTL representing the location of the incoming
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return address at the beginning of any function, before the prologue. This
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@ -1203,13 +1201,6 @@ enum reg_class
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REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
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} while (0)
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/* The register number for the return address register. For IA-64, this
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is not actually a pointer as the name suggests, but that's a name that
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gen_rtx_REG already takes care to keep unique. We modify
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return_address_pointer_rtx in ia64_expand_prologue to reference the
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final output regnum. */
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#define RETURN_ADDRESS_POINTER_REGNUM 329
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/* Register numbers used for passing a function's static chain pointer. */
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/* ??? The ABI sez the static chain should be passed as a normal parameter. */
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#define STATIC_CHAIN_REGNUM 15
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@ -1233,7 +1224,6 @@ enum reg_class
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{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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{RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
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}
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/* A C expression that returns nonzero if the compiler is allowed to try to
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@ -1879,8 +1869,8 @@ do { \
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"p60", "p61", "p62", "p63", \
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/* Branch registers. */ \
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"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
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/* Frame pointer. Return address. */ \
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"sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
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/* Frame pointer. Application registers. */ \
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"sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
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}
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/* If defined, a C initializer for an array of structures containing a name and
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@ -73,6 +73,7 @@
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(UNSPEC_BUNDLE_SELECTOR 23)
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(UNSPEC_ADDP4 24)
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(UNSPEC_PROLOGUE_USE 25)
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(UNSPEC_RET_ADDR 26)
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])
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(define_constants
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@ -410,6 +411,25 @@
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operands[3] = pic_offset_table_rtx;
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})
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;; This is used as a placeholder for the return address during early
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;; compilation. We won't know where we've placed this until during
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;; reload, at which point it can wind up in b0, a general register,
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;; or memory. The only safe destination under these conditions is a
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;; general register.
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(define_insn_and_split "*movdi_ret_addr"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
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""
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"#"
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"reload_completed"
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[(const_int 0)]
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{
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ia64_split_return_addr_rtx (operands[0]);
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DONE;
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}
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[(set_attr "itanium_class" "ialu")])
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(define_insn "*load_symptr_high"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
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Loading…
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