mips.c (override_options): Set MASK_BRANCHLIKELY in target_flags based on ISA...
2002-08-06 Chris Demetriou <cgd@broadcom.com> * config/mips/mips.c (override_options): Set MASK_BRANCHLIKELY in target_flags based on ISA, if it was not set on the command line. Warn if MASK_BRANCHLIKLEY is set but the ISA does not support Branch Likely instructions. * config/mips/mips.h (MASK_BRANCHLIKLEY): New macro. (TARGET_BRANCHLIKELY): Likewise. (TARGET_SWITCHES): Add -mbranch-likely and -mno-branch-likely. (GENERATE_BRANCHLIKELY): Use TARGET_BRANCHLIKELY rather than ISA_HAS_BRANCHLIKELY. (ISA_HAS_BRANCHLIKELY): Do not include MIPS16 check. * doc/invoke.texi: Document new MIPS -mbranch-likely and -mno-branch-likely options. From-SVN: r56088
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@ -1,3 +1,18 @@
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2002-08-06 Chris Demetriou <cgd@broadcom.com>
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* config/mips/mips.c (override_options): Set MASK_BRANCHLIKELY
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in target_flags based on ISA, if it was not set on the command
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line. Warn if MASK_BRANCHLIKLEY is set but the ISA does not
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support Branch Likely instructions.
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* config/mips/mips.h (MASK_BRANCHLIKLEY): New macro.
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(TARGET_BRANCHLIKELY): Likewise.
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(TARGET_SWITCHES): Add -mbranch-likely and -mno-branch-likely.
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(GENERATE_BRANCHLIKELY): Use TARGET_BRANCHLIKELY rather than
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ISA_HAS_BRANCHLIKELY.
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(ISA_HAS_BRANCHLIKELY): Do not include MIPS16 check.
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* doc/invoke.texi: Document new MIPS -mbranch-likely and
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-mno-branch-likely options.
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2002-08-06 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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* ip2k.c (ip2k_set_compare): Add missing iteration variable.
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@ -5177,6 +5177,31 @@ override_options ()
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if (mips_abi != ABI_32 && mips_abi != ABI_O64)
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flag_pcc_struct_return = 0;
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if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
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{
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/* If neither -mbranch-likely nor -mno-branch-likely was given
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on the command line, set MASK_BRANCHLIKELY based on the target
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architecture.
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By default, we enable use of Branch Likely instructions on
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all architectures which support them except for MIPS32 and MIPS64
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(i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
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implement them).
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The MIPS32 and MIPS64 architecture specifications say "Software
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is strongly encouraged to avoid use of Branch Likely
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instructions, as they will be removed from a future revision
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of the [MIPS32 and MIPS64] architecture." Therefore, we do not
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issue those instructions unless instructed to do so by
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-mbranch-likely. */
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if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS64))
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target_flags |= MASK_BRANCHLIKELY;
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else
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target_flags &= ~MASK_BRANCHLIKELY;
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}
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if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
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warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
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/* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
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to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
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/* ??? -non_shared turns off pic code generation, but this is not
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@ -232,6 +232,8 @@ extern void sbss_section PARAMS ((void));
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consts in rodata */
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#define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
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multiply-add operations. */
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#define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
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instructions. */
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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@ -322,6 +324,8 @@ extern void sbss_section PARAMS ((void));
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#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
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#define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
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#define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
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/* This is true if we must enable the assembly language file switching
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code. */
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@ -608,6 +612,10 @@ extern void sbss_section PARAMS ((void));
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N_("Trap on integer divide overflow")}, \
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{"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
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N_("Don't trap on integer divide overflow")}, \
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{ "branch-likely", MASK_BRANCHLIKELY, \
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N_("Use Branch Likely instructions, overriding default for arch")}, \
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{ "no-branch-likely", -MASK_BRANCHLIKELY, \
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N_("Don't use Branch Likely instructions, overriding default for arch")}, \
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{"debug", MASK_DEBUG, \
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NULL}, \
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{"debuga", MASK_DEBUG_A, \
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@ -741,7 +749,7 @@ extern void sbss_section PARAMS ((void));
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/* This is meant to be redefined in the host dependent files. */
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#define SUBTARGET_TARGET_OPTIONS
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#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
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#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
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/* Generate three-operand multiply instructions for SImode. */
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#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
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@ -776,8 +784,7 @@ extern void sbss_section PARAMS ((void));
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/* ISA has branch likely instructions (eg. mips2). */
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/* Disable branchlikely for tx39 until compare rewrite. They haven't
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been generated up to this point. */
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#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
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&& !TARGET_MIPS16)
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#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
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/* ISA has the conditional move instructions introduced in mips4. */
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#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
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@ -477,7 +477,8 @@ in the following sections.
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-m4650 -msingle-float -mmad @gol
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-mstats -EL -EB -G @var{num} -nocpp @gol
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-mabi=32 -mabi=n32 -mabi=64 -mabi=eabi @gol
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-mfix7000 -mno-crt0 -mflush-func=@var{func} -mno-flush-func}
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-mfix7000 -mno-crt0 -mflush-func=@var{func} -mno-flush-func
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-mbranch-likely -mno-branch-likely}
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@emph{i386 and x86-64 Options}
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@gccoptlist{
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@ -7369,6 +7370,18 @@ memory range for which the cache is being flushed, the size of the
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memory range, and the number 3 (to flush both caches). The default
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depends on the target gcc was configured for, but commonly is either
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@samp{_flush_func} or @samp{__cpu_flush}.
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@item -mbranch-likely
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@itemx -mno-branch-likely
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@opindex mbranch-likely
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@opindex mno-branch-likely
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Enable or disable use of Branch Likely instructions, regardless of the
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default for the selected architecture. By default, Branch Likely
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instructions may be generated if they are supported by the selected
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architecture. An exception is for the MIPS32 and MIPS64 architectures
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and processors which implement those architectures; for those, Branch
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Likely instructions will not be generated by default because the MIPS32
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and MIPS64 architectures specifically deprecate their use.
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@end table
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@node i386 and x86-64 Options
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