longlong.h (umul_ppmm): Remove SHMEDIA checks.
include/ * longlong.h (umul_ppmm): Remove SHMEDIA checks. (__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations. gcc/ * common/config/sh/sh-common.c (sh_option_optimization_table): Remove remaining SH5 related settings. * config/sh/sh-protos.h (shmedia_cleanup_truncate, shmedia_prepare_call_address): Delete. * config/sh/sh.c (sh_print_operand, output_stack_adjust, DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments. * config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC, UNSUPPORTED_SH2A): Remove m5 checks. (sh_divide_strategy_e): Remove SH5 division strategies. (TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default. * config/sh/sh.md (divsf3): Reinstate define_expand pattern. From-SVN: r235632
This commit is contained in:
Oleg Endo
parent
1ab06af64c
commit
af95276348
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@ -1,3 +1,17 @@
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2016-04-29 Oleg Endo <olegendo@gcc.gnu.org>
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* common/config/sh/sh-common.c (sh_option_optimization_table): Remove
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remaining SH5 related settings.
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* config/sh/sh-protos.h (shmedia_cleanup_truncate,
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shmedia_prepare_call_address): Delete.
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* config/sh/sh.c (sh_print_operand, output_stack_adjust,
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DWARF_CIE_DATA_ALIGNMENT, LOCAL_ALIGNMENT): Update comments.
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* config/sh/sh.h (SUBTARGET_ASM_RELAX_SPEC,
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UNSUPPORTED_SH2A): Remove m5 checks.
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(sh_divide_strategy_e): Remove SH5 division strategies.
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(TARGET_PTRMEMFUNC_VBIT_LOCATION): Remove and use default.
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* config/sh/sh.md (divsf3): Reinstate define_expand pattern.
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2016-04-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
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* config/s390/s390.c (s390_rtx_costs): Update documentation.
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@ -31,15 +31,8 @@ along with GCC; see the file COPYING3. If not see
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static const struct default_options sh_option_optimization_table[] =
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{
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{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
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{ OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_mdiv_, "inv:minlat", 1 },
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{ OPT_LEVELS_SIZE, OPT_mdiv_, SH_DIV_STR_FOR_SIZE, 1 },
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{ OPT_LEVELS_0_ONLY, OPT_mdiv_, "", 1 },
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/* We can't meaningfully test TARGET_SHMEDIA here, because -m
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options haven't been parsed yet, hence we'd read only the
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default. sh_target_reg_class will return NO_REGS if this is
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not SHMEDIA, so it's OK to always set
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flag_branch_target_load_optimize. */
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{ OPT_LEVELS_2_PLUS, OPT_fbranch_target_load_optimize, NULL, 1 },
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{ OPT_LEVELS_NONE, 0, NULL, 0 }
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};
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@ -392,11 +392,8 @@ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
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signed int, machine_mode);
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extern rtx sh_dwarf_register_span (rtx);
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extern int shmedia_cleanup_truncate (rtx);
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extern bool sh_contains_memref_p (rtx);
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extern bool sh_loads_bankedreg_p (rtx);
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extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
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extern int sh2a_get_function_vector_number (rtx);
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extern bool sh2a_is_function_vector_call (rtx);
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extern void sh_fix_range (const char *);
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@ -1177,9 +1177,6 @@ sh_print_operand (FILE *stream, rtx x, int code)
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output_addr_const (stream, x);
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break;
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/* N.B.: %R / %S / %T adjust memory addresses by four.
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For SHMEDIA, that means they can be used to access the first and
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second 32 bit part of a 64 bit (or larger) value that
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might be held in floating point registers or memory.
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While they can be used to access 64 bit parts of a larger value
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held in general purpose registers, that won't work with memory -
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neither for fp registers, since the frxx names are used. */
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@ -6748,15 +6745,12 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
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rtx adj_reg, tmp_reg, mem;
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/* If we reached here, the most likely case is the (sibcall)
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epilogue for non SHmedia. Put a special push/pop sequence
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for such case as the last resort. This looks lengthy but
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would not be problem because it seems to be very
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rare. */
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epilogue. Put a special push/pop sequence for such case as
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the last resort. This looks lengthy but would not be problem
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because it seems to be very rare. */
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gcc_assert (epilogue_p);
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/* ??? There is still the slight possibility that r4 or
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/* ??? There is still the slight possibility that r4 or
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r5 have been reserved as fixed registers or assigned
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as global registers, and they change during an
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interrupt. There are possible ways to handle this:
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@ -206,7 +206,7 @@ extern int code_for_indirect_jump_scratch;
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SUBTARGET_EXTRA_SPECS
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#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
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#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
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#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*::-isa=sh4-up}}}"
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#else
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#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
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#endif
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@ -250,7 +250,7 @@ extern int code_for_indirect_jump_scratch;
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/* Strict nofpu means that the compiler should tell the assembler
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to reject FPU instructions. E.g. from ASM inserts. */
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#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
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#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
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#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*::-isa=sh4-nofpu}}}}"
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#else
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#define SUBTARGET_ASM_ISA_SPEC \
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@ -299,7 +299,7 @@ extern int code_for_indirect_jump_scratch;
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#if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
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#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
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"%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
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"%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}"
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#else
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#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
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"%{m2a*:%eSH2a does not support little-endian}}"
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@ -323,17 +323,6 @@ extern int code_for_indirect_jump_scratch;
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extern int assembler_dialect;
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enum sh_divide_strategy_e {
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/* SH5 strategies. */
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SH_DIV_CALL,
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SH_DIV_CALL2,
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SH_DIV_FP, /* We could do this also for SH4. */
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SH_DIV_INV,
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SH_DIV_INV_MINLAT,
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SH_DIV_INV20U,
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SH_DIV_INV20L,
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SH_DIV_INV_CALL,
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SH_DIV_INV_CALL2,
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SH_DIV_INV_FP,
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/* SH1 .. SH4 strategies. Because of the small number of registers
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available, the compiler uses knowledge of the actual set of registers
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being clobbered by the different functions called. */
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@ -390,10 +379,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
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#define MIN_UNITS_PER_WORD 4
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/* Scaling factor for Dwarf data offsets for CFI information.
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The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
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SHmedia; however, since we do partial register saves for the registers
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visible to SHcompact, and for target registers for SHMEDIA32, we have
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to allow saves that are only 4-byte aligned. */
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The dwarf2out.c default would use -UNITS_PER_WORD. */
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#define DWARF_CIE_DATA_ALIGNMENT -4
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/* Width in bits of a pointer.
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@ -415,11 +401,6 @@ extern enum sh_divide_strategy_e sh_div_strategy;
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code of a function. */
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#define FUNCTION_BOUNDARY (16)
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/* On SH5, the lowest bit is used to indicate SHmedia functions, so
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the vbit must go into the delta field of
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pointers-to-member-functions. */
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#define TARGET_PTRMEMFUNC_VBIT_LOCATION (ptrmemfunc_vbit_in_pfn)
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/* Alignment of field after `int : 0' in a structure. */
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#define EMPTY_FIELD_BOUNDARY 32
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@ -437,9 +418,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
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/* get_mode_alignment assumes complex values are always held in multiple
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registers, but that is not the case on the SH; CQImode and CHImode are
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held in a single integer register. SH5 also holds CSImode and SCmode
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values in integer registers. This is relevant for argument passing on
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SHcompact as we use a stack temp in order to pass CSImode by reference. */
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held in a single integer register. */
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#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
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((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
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|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
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@ -9300,6 +9300,16 @@
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[(set_attr "type" "fp")
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(set_attr "fp_mode" "single")])
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(define_expand "divsf3"
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[(set (match_operand:SF 0 "fp_arith_reg_operand")
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(div:SF (match_operand:SF 1 "fp_arith_reg_operand")
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(match_operand:SF 2 "fp_arith_reg_operand")))]
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"TARGET_SH2E"
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{
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emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "divsf3_i"
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[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
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(div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
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@ -1,3 +1,8 @@
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2016-04-29 Oleg Endo <olegendo@gcc.gnu.org>
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* longlong.h (umul_ppmm): Remove SHMEDIA checks.
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(__umulsidi3, count_leading_zeros): Remove SHMEDIA implementations.
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2016-04-29 Claudiu Zissulescu <claziss@synopsys.com>
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* longlong.h (add_ssaaaa): Replace obsolete 'J' constraint with
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@ -1086,7 +1086,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
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} while (0)
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#endif
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#if defined(__sh__) && (!defined (__SHMEDIA__) || !__SHMEDIA__) && W_TYPE_SIZE == 32
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#if defined(__sh__) && W_TYPE_SIZE == 32
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#ifndef __sh1__
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ( \
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@ -1159,21 +1159,6 @@ extern UDItype __umulsidi3 (USItype, USItype);
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#endif /* __sh__ */
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#if defined (__SH5__) && defined (__SHMEDIA__) && __SHMEDIA__ && W_TYPE_SIZE == 32
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#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
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#define count_leading_zeros(count, x) \
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do \
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{ \
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UDItype x_ = (USItype)(x); \
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SItype c_; \
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\
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__asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
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(count) = c_ - 31; \
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} \
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while (0)
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#define COUNT_LEADING_ZEROS_0 32
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#endif
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#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
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&& W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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