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predicates.md (s5bit_cint_operand, [...]): New.

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* config/rs6000/predicates.md (s5bit_cint_operand,
        u5bit_cint_operand): New.
        * config/rs6000/altivec.md (altivec_vspltb, altivec_vsplth,
        altivec_vspltisw_v4sf): Use new 5 bit constant operand predicates.
        * config/rs6000/rs6000.c (rs6000_expand_unop_builtin): Fix signed
        5 bit constant check.

From-SVN: r101133
This commit is contained in:
Devang Patel 2005-06-17 13:30:42 -07:00 committed by Devang Patel
parent 599c25e213
commit afca671b78
4 changed files with 26 additions and 7 deletions
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9
gcc/ChangeLog
View File

@ -1,3 +1,12 @@
2005-06-17 Devang Patel <dpatel@apple.com>
* config/rs6000/predicates.md (s5bit_cint_operand,
u5bit_cint_operand): New.
* config/rs6000/altivec.md (altivec_vspltb, altivec_vsplth,
altivec_vspltisw_v4sf): Use new 5 bit constant operand predicates.
* config/rs6000/rs6000.c (rs6000_expand_unop_builtin): Fix signed
5 bit constant check.
2005-06-17 Richard Henderson <rth@redhat.com>
* local-alloc.c (update_equiv_regs): Update reg_equiv_init

10
gcc/config/rs6000/altivec.md
View File

@ -1167,7 +1167,7 @@
(vec_duplicate:V16QI
(vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
(parallel
[(match_operand:QI 2 "immediate_operand" "i")]))))]
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
"TARGET_ALTIVEC"
"vspltb %0,%1,%2"
[(set_attr "type" "vecperm")])
@ -1177,7 +1177,7 @@
(vec_duplicate:V8HI
(vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
(parallel
[(match_operand:QI 2 "immediate_operand" "i")]))))]
[(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
"TARGET_ALTIVEC"
"vsplth %0,%1,%2"
[(set_attr "type" "vecperm")])
@ -1187,7 +1187,7 @@
(vec_duplicate:V4SI
(vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
(parallel
[(match_operand:QI 2 "immediate_operand" "i")]))))]
[(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
"TARGET_ALTIVEC"
"vspltw %0,%1,%2"
[(set_attr "type" "vecperm")])
@ -1195,7 +1195,7 @@
(define_insn "altivec_vspltis<VI_char>"
[(set (match_operand:VI 0 "register_operand" "=v")
(vec_duplicate:VI
(match_operand:QI 1 "const_int_operand" "i")))]
(match_operand:QI 1 "s5bit_cint_operand" "i")))]
"TARGET_ALTIVEC"
"vspltis<VI_char> %0,%1"
[(set_attr "type" "vecperm")])
@ -1203,7 +1203,7 @@
(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_duplicate:V4SF
(float:SF (match_operand:QI 1 "const_int_operand" "i"))))]
(float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))]
"TARGET_ALTIVEC"
"vspltisw %0,%1"
[(set_attr "type" "vecperm")])

10
gcc/config/rs6000/predicates.md
View File

@ -44,6 +44,16 @@
(and (match_code "reg")
(match_test "XER_REGNO_P (REGNO (op))")))
;; Return 1 if op is a signed 5-bit constant integer.
(define_predicate "s5bit_cint_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
;; Return 1 if op is a unsigned 5-bit constant integer.
(define_predicate "u5bit_cint_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
;; Return 1 if op is a signed 8-bit constant integer.
;; Integer multiplcation complete more quickly
(define_predicate "s8bit_cint_operand"

4
gcc/config/rs6000/rs6000.c
View File

@ -6241,8 +6241,8 @@ rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
{
/* Only allow 5-bit *signed* literals. */
if (GET_CODE (op0) != CONST_INT
|| INTVAL (op0) > 0x1f
|| INTVAL (op0) < -0x1f)
|| INTVAL (op0) > 15
|| INTVAL (op0) < -16)
{
error ("argument 1 must be a 5-bit signed literal");
return const0_rtx;