avr-protos.h (avr_output_bld): New.
* config/avr/avr-protos.h (avr_output_bld): New. (out_shift_with_cnt): Add t_len argument. * config/avr/avr.c (avr_num_arg_regs): Remove -mpack-args. (output_movqi, output_movhi, output_movsisf): Optimize loading any constant with exactly one bit set to NO_LD_REGS. (out_shift_with_cnt): Optimize output code for size or speed, depending on optimize_size. Handle small shift counts as well (if not hand-optimized in ?sh??i3_out). Shifts can be done with or without a scratch register, with help of __tmp_reg__ or __zero_reg__ if necessary. Add T_LEN argument to pass the length of TEMPLATE in words, return total insn length in *LEN. (ashlqi3_out, ashrqi3_out, lshrqi3_out): Change all calls to out_shift_with_cnt to work with the above change. (ashlhi3_out, ashlsi3_out, ashrhi3_out, ashrsi3_out, lshrhi3_out, lshrsi3_out): Likewise. Optimize more known shift count cases. Remove cases already well optimized in out_shift_with_cnt. (avr_output_bld): New function. * config/avr/avr.h (MASK_PACK_ARGS, TARGET_PACK_ARGS): Remove. (TARGET_SWITCHES): Remove -mpack-args backward compatibility. * config/avr/avr.md (*reload_inqi, *reload_inhi, *reload_insi): Add reload_completed to insn condition - only for peepholes. (ashlqi3, ashrqi3, lshrqi3): Correct insn length for shift counts in a register or memory. (ashlhi3, ashlsi3, ashrhi3, ashrsi3, lshrhi3, lshrsi3): Likewise. Do not require a scratch register. (*ashlhi3_const, *ashlsi3_const, *ashrhi3_const, *ashrsi3_const, *lshrhi3_const, *lshrsi3_const): New insns and matching peepholes. Optimize shifts by known count using a scratch register, but only if one is still available after register allocation. From-SVN: r36963
This commit is contained in:
Marek Michalkiewicz
Denis Chertykov
parent
406b0a7cd6
commit
afee2a52da
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@ -1,3 +1,35 @@
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2000-10-14 Marek Michalkiewicz <marekm@linux.org.pl>
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* config/avr/avr-protos.h (avr_output_bld): New.
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(out_shift_with_cnt): Add t_len argument.
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* config/avr/avr.c (avr_num_arg_regs): Remove -mpack-args.
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(output_movqi, output_movhi, output_movsisf): Optimize loading
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any constant with exactly one bit set to NO_LD_REGS.
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(out_shift_with_cnt): Optimize output code for size or speed,
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depending on optimize_size. Handle small shift counts as well
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(if not hand-optimized in ?sh??i3_out). Shifts can be done
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with or without a scratch register, with help of __tmp_reg__
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or __zero_reg__ if necessary. Add T_LEN argument to pass the
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length of TEMPLATE in words, return total insn length in *LEN.
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(ashlqi3_out, ashrqi3_out, lshrqi3_out): Change all calls to
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out_shift_with_cnt to work with the above change.
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(ashlhi3_out, ashlsi3_out, ashrhi3_out, ashrsi3_out, lshrhi3_out,
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lshrsi3_out): Likewise. Optimize more known shift count cases.
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Remove cases already well optimized in out_shift_with_cnt.
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(avr_output_bld): New function.
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* config/avr/avr.h (MASK_PACK_ARGS, TARGET_PACK_ARGS): Remove.
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(TARGET_SWITCHES): Remove -mpack-args backward compatibility.
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* config/avr/avr.md (*reload_inqi, *reload_inhi, *reload_insi):
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Add reload_completed to insn condition - only for peepholes.
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(ashlqi3, ashrqi3, lshrqi3): Correct insn length for shift counts
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in a register or memory.
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(ashlhi3, ashlsi3, ashrhi3, ashrsi3, lshrhi3, lshrsi3): Likewise.
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Do not require a scratch register.
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(*ashlhi3_const, *ashlsi3_const, *ashrhi3_const, *ashrsi3_const,
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*lshrhi3_const, *lshrsi3_const): New insns and matching peepholes.
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Optimize shifts by known count using a scratch register, but only
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if one is still available after register allocation.
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2000-10-20 J. David Anglin <dave@hiauly1.hia.nrc.ca>
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* t-vax: New file. Don't build modules from libgcc1.c.
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@ -109,6 +109,8 @@ extern const char * lshrqi3_out PARAMS ((rtx insn, rtx operands[], int *len));
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extern const char * lshrhi3_out PARAMS ((rtx insn, rtx operands[], int *len));
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extern const char * lshrsi3_out PARAMS ((rtx insn, rtx operands[], int *len));
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extern void avr_output_bld PARAMS ((rtx operands[], int bit_nr));
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extern enum reg_class preferred_reload_class PARAMS ((rtx x,
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enum reg_class class));
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extern int avr_address_cost PARAMS ((rtx x));
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@ -150,7 +152,8 @@ extern int avr_simplify_comparision_p PARAMS ((enum machine_mode mode,
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extern RTX_CODE avr_normalize_condition PARAMS ((RTX_CODE condition));
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extern int compare_eq_p PARAMS ((rtx insn));
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extern void out_shift_with_cnt PARAMS ((const char *template, rtx insn,
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rtx operands[], int *len));
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rtx operands[], int *len,
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int t_len));
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extern int const_int_pow2_p PARAMS ((rtx x));
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#endif /* RTX_CODE */
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File diff suppressed because it is too large
Load Diff
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@ -55,7 +55,6 @@ extern int target_flags;
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#define MASK_NO_INTERRUPTS 0x00020000
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#define MASK_CALL_PROLOGUES 0x00040000
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#define MASK_TINY_STACK 0x00080000
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#define MASK_PACK_ARGS 0x00100000
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#define TARGET_ORDER_1 (target_flags & MASK_ORDER_1)
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#define TARGET_ORDER_2 (target_flags & MASK_ORDER_2)
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@ -64,7 +63,6 @@ extern int target_flags;
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#define TARGET_INSN_SIZE_DUMP (target_flags & MASK_INSN_SIZE_DUMP)
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#define TARGET_CALL_PROLOGUES (target_flags & MASK_CALL_PROLOGUES)
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#define TARGET_TINY_STACK (target_flags & MASK_TINY_STACK)
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#define TARGET_PACK_ARGS (target_flags & MASK_PACK_ARGS)
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/* Dump each assembler insn's rtl into the output file.
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This is for debugging the compiler itself. */
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@ -104,8 +102,6 @@ extern int target_flags;
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N_("Use subroutines for function prologue/epilogue") }, \
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{ "tiny-stack", MASK_TINY_STACK, \
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N_("Change only the low 8 bits of the stack pointer") }, \
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{ "pack-args", MASK_PACK_ARGS, \
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N_("Do not align function arguments on even numbered registers") }, \
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{ "rtl", MASK_RTL_DUMP, NULL }, \
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{ "size", MASK_INSN_SIZE_DUMP, \
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N_("Output instruction sizes to the asm file") }, \
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@ -182,7 +182,7 @@
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[(set (match_operand:QI 0 "register_operand" "=l")
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(match_operand:QI 1 "immediate_operand" "i"))
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(clobber (match_operand:QI 2 "register_operand" "=&d"))]
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""
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"reload_completed"
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"ldi %2,lo8(%1)
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mov %0,%2"
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[(set_attr "length" "2")
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@ -231,7 +231,7 @@
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[(set (match_operand:HI 0 "register_operand" "=r")
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(match_operand:HI 1 "immediate_operand" "i"))
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(clobber (match_operand:QI 2 "register_operand" "=&d"))]
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""
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"reload_completed"
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"* return output_reload_inhi (insn, operands, NULL);"
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[(set_attr "length" "4")
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(set_attr "cc" "none")])
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@ -279,7 +279,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "immediate_operand" "i"))
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(clobber (match_operand:QI 2 "register_operand" "=&d"))]
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""
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"reload_completed"
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"* return output_reload_insisf (insn, operands, NULL);"
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[(set_attr "length" "8")
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(set_attr "cc" "none")])
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@ -889,34 +889,74 @@
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;; arithmetic shift left
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(define_insn "ashlqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,n,n,Qm")))]
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
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""
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"* return ashlqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,4,6,7")
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(set_attr "cc" "clobber,set_czn,set_czn,clobber")])
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[(set_attr "length" "5,1,2,4,6,9")
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(set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
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(define_insn "ashlhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,i,Qm")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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""
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"* return ashlhi3_out (insn, operands, NULL);"
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[(set_attr "length" "7,2,2,4,5,8")
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[(set_attr "length" "6,2,2,4,10,10")
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(set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
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(define_insn "ashlsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,i,Qm")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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""
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"* return ashlsi3_out (insn, operands, NULL);"
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[(set_attr "length" "9,4,4,8,7,10")
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[(set_attr "length" "8,4,4,8,10,12")
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(set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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(ashift:HI (match_operand:HI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"")
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(define_insn "*ashlhi3_const"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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"reload_completed"
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"* return ashlhi3_out (insn, operands, NULL);"
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[(set_attr "length" "2,2,4,10")
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(set_attr "cc" "set_n,clobber,set_n,clobber")])
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:SI 0 "register_operand" "")
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(ashift:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"")
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(define_insn "*ashlsi3_const"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,r,0")
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(match_operand:QI 2 "const_int_operand" "P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,&d"))]
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"reload_completed"
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"* return ashlsi3_out (insn, operands, NULL);"
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[(set_attr "length" "4,4,10")
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(set_attr "cc" "set_n,clobber,clobber")])
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;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
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;; arithmetic shift right
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@ -926,61 +966,141 @@
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(match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
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""
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"* return ashrqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,1,2,5,7")
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(set_attr "cc" "clobber,set_zn,set_zn,clobber,clobber")])
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[(set_attr "length" "5,1,2,5,9")
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(set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])
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(define_insn "ashrhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0")
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(match_operand:QI 2 "general_operand" "r,P,K,O,i,Qm")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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""
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"* return ashrhi3_out (insn, operands, NULL);"
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[(set_attr "length" "7,2,4,4,5,8")
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(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
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[(set_attr "length" "6,2,4,4,10,10")
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(set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
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(define_insn "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,i,Qm")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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""
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"* return ashrsi3_out (insn, operands, NULL);"
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[(set_attr "length" "9,4,6,8,7,10")
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(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
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[(set_attr "length" "8,4,6,8,10,12")
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(set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:HI 0 "register_operand" "")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"")
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(define_insn "*ashrhi3_const"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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"reload_completed"
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"* return ashrhi3_out (insn, operands, NULL);"
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[(set_attr "length" "2,4,4,10")
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(set_attr "cc" "clobber,set_n,clobber,clobber")])
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(define_peephole2
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[(match_scratch:QI 3 "d")
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(set (match_operand:SI 0 "register_operand" "")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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""
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[(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
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(clobber (match_dup 3))])]
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"")
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(define_insn "*ashrsi3_const"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
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(match_operand:QI 2 "const_int_operand" "P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,&d"))]
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"reload_completed"
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"* return ashrsi3_out (insn, operands, NULL);"
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[(set_attr "length" "4,4,10")
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(set_attr "cc" "clobber,set_n,clobber")])
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;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
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;; logical shift right
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(define_insn "lshrqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
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(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,n,n,Qm")))]
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
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(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
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""
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"* return lshrqi3_out (insn, operands, NULL);"
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[(set_attr "length" "6,4,6,7")
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(set_attr "cc" "clobber,set_czn,set_czn,clobber")])
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[(set_attr "length" "5,1,2,4,6,9")
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(set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
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(define_insn "lshrhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,K,O,i,Qm")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
|
||||
""
|
||||
"* return lshrhi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "7,2,4,2,5,8")
|
||||
[(set_attr "length" "6,2,2,4,10,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,O,K,i,Qm")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,X,&d,X"))]
|
||||
(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
|
||||
""
|
||||
"* return lshrsi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "9,4,4,8,7,10")
|
||||
[(set_attr "length" "8,4,4,8,10,12")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
|
||||
|
||||
;; Optimize if a scratch register from LD_REGS happens to be available.
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:QI 3 "d")
|
||||
(set (match_operand:HI 0 "register_operand" "")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "")
|
||||
(match_operand:QI 2 "const_int_operand" "")))]
|
||||
""
|
||||
[(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_dup 3))])]
|
||||
"")
|
||||
|
||||
(define_insn "*lshrhi3_const"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
|
||||
(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
||||
"reload_completed"
|
||||
"* return lshrhi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "2,2,4,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber")])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:QI 3 "d")
|
||||
(set (match_operand:SI 0 "register_operand" "")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:QI 2 "const_int_operand" "")))]
|
||||
""
|
||||
[(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_dup 3))])]
|
||||
"")
|
||||
|
||||
(define_insn "*lshrsi3_const"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
|
||||
(match_operand:QI 2 "const_int_operand" "P,O,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,&d"))]
|
||||
"reload_completed"
|
||||
"* return lshrsi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "4,4,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber")])
|
||||
|
||||
;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
|
||||
;; abs
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue