From b0a71a184c6e2ec2cdf5eed90308d4e96fb1beda Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 5 Dec 2019 13:02:57 +0000 Subject: [PATCH] re PR tree-optimization/92818 (Typo in vec_perm -> bit_insert pattern) 2019-12-05 Richard Biener PR middle-end/92818 * tree-ssa-forwprop.c (simplify_vector_constructor): Improve heuristics on what don't care element to choose. * match.pd (VEC_PERM_EXPR -> BIT_INSERT_EXPR): Fix typo. * gcc.target/i386/pr92818.c: New testcase. From-SVN: r278998 --- gcc/ChangeLog | 7 +++++++ gcc/match.pd | 2 +- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr92818.c | 14 ++++++++++++++ gcc/tree-ssa-forwprop.c | 7 +++++-- 5 files changed, 32 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr92818.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fa926137255..4a894859761 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-12-05 Richard Biener + + PR middle-end/92818 + * tree-ssa-forwprop.c (simplify_vector_constructor): Improve + heuristics on what don't care element to choose. + * match.pd (VEC_PERM_EXPR -> BIT_INSERT_EXPR): Fix typo. + 2019-12-05 Martin Liska PR gcov-profile/92817 diff --git a/gcc/match.pd b/gcc/match.pd index c50b5468c74..68027f6757d 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -6049,7 +6049,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) break; if (at < encoded_nelts && sel.series_p (at + 1, 1, at + 1, 1)) { - if (known_lt (at, nelts)) + if (known_lt (poly_uint64 (sel[at]), nelts)) ins = fold_read_from_vector (cop0, sel[at]); else ins = fold_read_from_vector (cop1, sel[at] - nelts); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d58bb050460..900e3bece8c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-12-05 Richard Biener + + PR middle-end/92818 + * gcc.target/i386/pr92818.c: New testcase. + 2019-12-05 Frederik Harwath * gcc.dg/asm-4.c: Skip on target amdgcn-*-*. diff --git a/gcc/testsuite/gcc.target/i386/pr92818.c b/gcc/testsuite/gcc.target/i386/pr92818.c new file mode 100644 index 00000000000..c138e24b4f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr92818.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx2 -fdump-tree-forwprop1" } */ + +typedef double v4df __attribute__((vector_size (32))); +typedef double v2df __attribute__((vector_size (16))); + +v2df +bar (v4df x, double *p) +{ + return (v2df) { x[0], *p }; +} + +/* { dg-final { scan-tree-dump "BIT_INSERT_EXPR" "forwprop1" } } */ +/* { dg-final { scan-assembler "movhpd" } } */ diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index a27a4cfb379..2f9b0893221 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -2265,9 +2265,12 @@ simplify_vector_constructor (gimple_stmt_iterator *gsi) sel.quick_push (elts[i].second + elts[i].first * refnelts); /* And fill the tail with "something". It's really don't care, and ideally we'd allow VEC_PERM to have a smaller destination - vector. */ + vector. As heuristic try to preserve a uniform orig[0] which + facilitates later pattern-matching VEC_PERM_EXPR to a + BIT_INSERT_EXPR. */ for (; i < refnelts; ++i) - sel.quick_push (i - elts.length ()); + sel.quick_push ((elts[0].second == 0 && elts[0].first == 0 + ? 0 : refnelts) + i); vec_perm_indices indices (sel, orig[1] ? 2 : 1, refnelts); if (!can_vec_perm_const_p (TYPE_MODE (perm_type), indices)) return false;