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xlr.md (ir_xlr_alu_clz): New insn_reservation. 

2012-08-04  Catherine Moore  <clm@codesourcery.com>
	    Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation.
	(ir_xlr_alu): Remove clz.
	* config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY.

Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>

From-SVN: r190146
This commit is contained in:
Catherine Moore 2012-08-04 18:16:57 -04:00 committed by Sandra Loosemore
parent b6f1f6eaed
commit b0e7f54dc7
3 changed files with 14 additions and 2 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2012-08-04 Catherine Moore <clm@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
* config/mips/xlr.md (ir_xlr_alu_clz): New insn_reservation.
(ir_xlr_alu): Remove clz.
* config/mips/mips-cpus.def (xlr): Set PTF_AVOID_BRANCHLIKELY.
2012-08-04 Richard Earnshaw <rearnsha@arm.com>
* arm.c (arm_gen_constant): Use SImode when preparing operands for

2
gcc/config/mips/mips-cpus.def
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@ -142,7 +142,7 @@ MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0)
MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */

7
gcc/config/mips/xlr.md
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@ -28,10 +28,15 @@
(eq_attr "type" "slt"))
"xlr_main_pipe")
(define_insn_reservation "ir_xlr_alu_clz" 2
(and (eq_attr "cpu" "xlr")
(eq_attr "type" "clz"))
"xlr_main_pipe")
;; Integer arithmetic instructions.
(define_insn_reservation "ir_xlr_alu" 1
(and (eq_attr "cpu" "xlr")
(eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop"))
(eq_attr "type" "move,arith,shift,logical,signext,const,unknown,multi,nop,trap,atomic,syncloop"))
"xlr_main_pipe")
;; Integer arithmetic instructions.