arm.c (arm_arch5e): New variable.
* arm.c (arm_arch5e): New variable. (all_cores): XScale is a 5TE device. (arm_override_options): Set arm_arch5e. (arm_init_builtins): __builtin_prefetch is in arch5e. * arm.h (arm_arch5e): Declare it. * arm.h (PREDICATE_CODES): Add arm_hard_register_operand. * arm.md (define_constants): Add defines for UNSPEC and UNSPEC_VOLATILE insns. Update all users. (define_constants): Add constants for IP_REGNUM, SP_REGNUM, PC_REGNUM. * arm.c (multi_register_push, note_invalid_constants) (emit_multi_reg_push, emit_sfm, expand_prologue): Use constants. * arm.h (SP_REGNUM, IP_REGNUM, PC_REGNUM): Delete defines. (STACK_POINTER_REGNUM): Define in terms of SP_REGNUM. From-SVN: r38803
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
261efdefd0
commit
b15bca310f
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@ -1,3 +1,21 @@
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2001-01-08 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (arm_arch5e): New variable.
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(all_cores): XScale is a 5TE device.
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(arm_override_options): Set arm_arch5e.
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(arm_init_builtins): __builtin_prefetch is in arch5e.
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* arm.h (arm_arch5e): Declare it.
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* arm.h (PREDICATE_CODES): Add arm_hard_register_operand.
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* arm.md (define_constants): Add defines for UNSPEC and
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UNSPEC_VOLATILE insns. Update all users.
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(define_constants): Add constants for IP_REGNUM, SP_REGNUM, PC_REGNUM.
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* arm.c (multi_register_push, note_invalid_constants)
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(emit_multi_reg_push, emit_sfm, expand_prologue): Use constants.
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* arm.h (SP_REGNUM, IP_REGNUM, PC_REGNUM): Delete defines.
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(STACK_POINTER_REGNUM): Define in terms of SP_REGNUM.
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Mon Jan 8 16:14:56 MET 2001 Jan Hubicka <jh@suse.cz>
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* jump.c (jump_optimize_1): Use reversed_comparison_code
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@ -151,7 +151,7 @@ int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
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#define FL_THUMB (1 << 6) /* Thumb aware */
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#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
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#define FL_STRONG (1 << 8) /* StrongARM */
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#define FL_ARCH5E (1 << 9) /* El Segundo extenstions to v5 */
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#define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
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#define FL_XSCALE (1 << 10) /* XScale */
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/* The bits in this mask specify which instructions we are
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@ -176,6 +176,9 @@ int arm_arch4 = 0;
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/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
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int arm_arch5 = 0;
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/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
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int arm_arch5e = 0;
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/* Nonzero if this chip can benefit from load scheduling. */
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int arm_ld_sched = 0;
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@ -279,7 +282,7 @@ static struct processors all_cores[] =
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{"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
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{"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
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{"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
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{"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 },
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{"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 | FL_ARCH5E },
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{NULL, 0}
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};
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@ -586,6 +589,7 @@ arm_override_options ()
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arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
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arm_arch4 = (insn_flags & FL_ARCH4) != 0;
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arm_arch5 = (insn_flags & FL_ARCH5) != 0;
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arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
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arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
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arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
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@ -4054,7 +4058,7 @@ multi_register_push (op, mode)
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if (GET_CODE (op) != PARALLEL
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|| (GET_CODE (XVECEXP (op, 0, 0)) != SET)
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|| (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
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|| (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
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|| (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
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return 0;
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return 1;
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@ -5888,7 +5892,7 @@ note_invalid_constants (insn, address)
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this shouldn't be needed any more. */
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#ifndef AOF_ASSEMBLER
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/* XXX Is this still needed? */
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else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
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else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
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push_minipool_fix (insn, address, recog_data.operand_loc[opno],
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recog_data.operand_mode[opno],
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XVECEXP (op, 0, 0));
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@ -7593,7 +7597,8 @@ emit_multi_reg_push (mask)
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something like this:
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(parallel [
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(set (mem:BLK (pre_dec:BLK (reg:SI sp))) (unspec:BLK [(reg:SI r4)] 2))
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(set (mem:BLK (pre_dec:BLK (reg:SI sp)))
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(unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
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(use (reg:SI 11 fp))
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(use (reg:SI 12 ip))
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(use (reg:SI 14 lr))
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@ -7708,7 +7713,7 @@ emit_sfm (base_reg, count)
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gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
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gen_rtx_UNSPEC (BLKmode,
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gen_rtvec (1, reg),
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2));
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UNSPEC_PUSH_MULT));
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tmp
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= gen_rtx_SET (VOIDmode,
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gen_rtx_MEM (XFmode,
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@ -7941,7 +7946,8 @@ arm_expand_prologue ()
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{
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rtx unspec = gen_rtx_UNSPEC (SImode,
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gen_rtvec (2, stack_pointer_rtx,
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hard_frame_pointer_rtx), 4);
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hard_frame_pointer_rtx),
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UNSPEC_PRLG_STK);
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insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
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gen_rtx_MEM (BLKmode, unspec)));
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@ -8801,6 +8807,11 @@ arm_init_builtins ()
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if (arm_arch5)
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{
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def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
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}
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/* Initialize arm V5E builtins. */
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if (arm_arch5e)
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{
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def_builtin ("__builtin_prefetch", void_ftype_pchar,
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ARM_BUILTIN_PREFETCH);
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}
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@ -561,6 +561,9 @@ extern int arm_arch4;
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/* Nonzero if this chip supports the ARM Architecture 5 extensions */
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extern int arm_arch5;
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/* Nonzero if this chip supports the ARM Architecture 5E extensions */
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extern int arm_arch5e;
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/* Nonzero if this chip can benefit from load scheduling. */
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extern int arm_ld_sched;
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@ -931,32 +934,21 @@ extern const char * structure_size_string;
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pointer. */
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#define ARM_HARD_FRAME_POINTER_REGNUM 11
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#define THUMB_HARD_FRAME_POINTER_REGNUM 7
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#define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
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#define HARD_FRAME_POINTER_REGNUM \
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(TARGET_ARM \
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? ARM_HARD_FRAME_POINTER_REGNUM \
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: THUMB_HARD_FRAME_POINTER_REGNUM)
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#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
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/* Scratch register - used in all kinds of places, eg trampolines. */
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#define IP_REGNUM 12
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM 13
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#define SP_REGNUM STACK_POINTER_REGNUM
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/* Register which holds return address from a subroutine call. */
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#define LR_REGNUM 14
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/* Define this if the program counter is overloaded on a register. */
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#define PC_REGNUM 15
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/* The number of the last ARM (integer) register. */
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#define LAST_ARM_REGNUM 15
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#define STACK_POINTER_REGNUM SP_REGNUM
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/* ARM floating pointer registers. */
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#define FIRST_ARM_FP_REGNUM 16
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#define LAST_ARM_FP_REGNUM 23
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/* Internal, so that we don't need to refer to a raw number */
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#define CC_REGNUM 24
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM 25
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@ -2949,6 +2941,7 @@ extern int making_const_table;
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/* Define the codes that are matched by predicates in arm.c */
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#define PREDICATE_CODES \
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{"s_register_operand", {SUBREG, REG}}, \
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{"arm_hard_register_operand", {REG}}, \
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{"f_register_operand", {SUBREG, REG}}, \
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{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
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{"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
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@ -28,31 +28,72 @@
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;; Unfortunately RISC iX doesn't work well with these so they are disabled.
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;; (See arm.h)
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;;---------------------------------------------------------------------------
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;; Constants
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;; Register numbers
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(define_constants
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[(IP_REGNUM 12) ; Scratch register
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(SP_REGNUM 13) ; Stack pointer
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(LR_REGNUM 14) ; Return address register
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(PC_REGNUM 15) ; Program counter
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(CC_REGNUM 24) ; Condition code pseudo register
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(LAST_ARM_REGNUM 15)
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]
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)
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;; UNSPEC Usage:
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;; 0 `sin' operation: operand 0 is the result, operand 1 the parameter,
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;; the mode is MODE_FLOAT
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;; 1 `cos' operation: operand 0 is the result, operand 1 the parameter,
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;; the mode is MODE_FLOAT
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;; 2 `push multiple' operation: operand 0 is the first register. Subsequent
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;; registers are in parallel (use...) expressions.
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;; 3 A symbol that has been treated properly for pic usage, that is, we
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;; will add the pic_register value to it before trying to dereference it.
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;; Note: sin and cos are no-longer used.
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;;
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(define_constants
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[(UNSPEC_SIN 0) ; `sin' operation (MODE_FLOAT):
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; operand 0 is the result,
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; operand 1 the parameter.
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(UNPSEC_COS 1) ; `cos' operation (MODE_FLOAT):
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; operand 0 is the result,
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; operand 1 the parameter.
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(UNSPEC_PUSH_MULT 2) ; `push multiple' operation:
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; operand 0 is the first register,
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; subsequent registers are in parallel (use ...)
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; expressions.
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(UNSPEC_PIC_SYM 3) ; A symbol that has been treated properly for pic
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; usage, that is, we will add the pic_register
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; value to it before trying to dereference it.
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(UNSPEC_PRLG_STK 4) ; A special barrier that prevents frame accesses
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; being scheduled before the stack adjustment insn.
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(UNSPEC_CLZ 5) ; `clz' instruction, count leading zeros (SImode):
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; operand 0 is the result,
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; operand 1 is the parameter.
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]
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)
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;; UNSPEC_VOLATILE Usage:
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;; 0 `blockage' insn to prevent scheduling across an insn in the code.
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;; 1 `epilogue' insn, used to represent any part of the instruction epilogue
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;; sequence that isn't expanded into normal RTL. Used for both normal
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;; and sibcall epilogues.
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;; 2 `align' insn. Used at the head of a minipool table for inlined
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;; constants.
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;; 3 `end-of-table'. Used to mark the end of a minipool table.
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;; 4 `pool-entry(1)'. An entry in the constant pool for an 8-bit object.
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;; 5 `pool-entry(2)'. An entry in the constant pool for a 16-bit object.
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;; 6 `pool-entry(4)'. An entry in the constant pool for a 32-bit object.
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;; 7 `pool-entry(8)'. An entry in the constant pool for a 64-bit object.
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;;
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(define_constants
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[(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
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; insn in the code.
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(VUNSPEC_EPILOGUE 1) ; `epilogue' insn, used to represent any part of the
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; instruction epilogue sequence that isn't expanded
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; into normal RTL. Used for both normal and sibcall
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; epilogues.
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(VUNSPEC_ALIGN 2) ; `align' insn. Used at the head of a minipool table
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; for inlined constants.
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(VUNSPEC_POOL_END 3) ; `end-of-table'. Used to mark the end of a minipool
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; table.
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(VUNSPEC_POOL_1 4) ; `pool-entry(1)'. An entry in the constant pool for
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; an 8-bit object.
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(VUNSPEC_POOL_2 5) ; `pool-entry(2)'. An entry in the constant pool for
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; a 16-bit object.
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(VUNSPEC_POOL_4 6) ; `pool-entry(4)'. An entry in the constant pool for
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; a 32-bit object.
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(VUNSPEC_POOL_8 7) ; `pool-entry(8)'. An entry in the constant pool for
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; a 64-bit object.
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(VUNSPEC_PREFETCH 8) ; `pld' insn to prefetch a cache line:
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; operand 0 is the address to fetch.
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]
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)
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;;---------------------------------------------------------------------------
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;; Attributes
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; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when
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@ -345,14 +386,8 @@
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(eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32)
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;;---------------------------------------------------------------------------
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;; Make code more maintainable by using names for fixed registers.
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(define_constants
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[(LR_REGNUM 14)
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(LAST_ARM_REGNUM 15)
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(CC_REGNUM 24)]
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)
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;; Insn patterns
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;;
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;; Addition insns.
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;; Note: For DImode insns, there is normally no reason why operands should
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@ -2869,14 +2904,16 @@
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;; to always call a library function.
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;(define_insn "sinsf2"
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; [(set (match_operand:SF 0 "s_register_operand" "=f")
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; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 0))]
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; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")]
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; UNSPEC_SIN))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "sin%?s\\t%0, %1"
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;[(set_attr "type" "float_em")])
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;
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;(define_insn "sindf2"
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; [(set (match_operand:DF 0 "s_register_operand" "=f")
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; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 0))]
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; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")]
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; UNSPEC_SIN))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "sin%?d\\t%0, %1"
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;[(set_attr "type" "float_em")])
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@ -2884,28 +2921,32 @@
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;(define_insn "*sindf_esfdf"
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; [(set (match_operand:DF 0 "s_register_operand" "=f")
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; (unspec:DF [(float_extend:DF
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; (match_operand:SF 1 "s_register_operand" "f"))] 0))]
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; (match_operand:SF 1 "s_register_operand" "f"))]
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; UNSPEC_SIN))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "sin%?d\\t%0, %1"
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;[(set_attr "type" "float_em")])
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;
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;(define_insn "sinxf2"
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; [(set (match_operand:XF 0 "s_register_operand" "=f")
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; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 0))]
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; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")]
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; UNSPEC_SIN))]
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; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
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; "sin%?e\\t%0, %1"
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;[(set_attr "type" "float_em")])
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;
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;(define_insn "cossf2"
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; [(set (match_operand:SF 0 "s_register_operand" "=f")
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; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 1))]
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; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")]
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; UNSPEC_COS))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "cos%?s\\t%0, %1"
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;[(set_attr "type" "float_em")])
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;
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;(define_insn "cosdf2"
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; [(set (match_operand:DF 0 "s_register_operand" "=f")
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; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 1))]
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; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")]
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; UNSPEC_COS))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "cos%?d\\t%0, %1"
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;[(set_attr "type" "float_em")])
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@ -2913,14 +2954,16 @@
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;(define_insn "*cosdf_esfdf"
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; [(set (match_operand:DF 0 "s_register_operand" "=f")
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; (unspec:DF [(float_extend:DF
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; (match_operand:SF 1 "s_register_operand" "f"))] 1))]
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; (match_operand:SF 1 "s_register_operand" "f"))]
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; UNSPEC_COS))]
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; "TARGET_ARM && TARGET_HARD_FLOAT"
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; "cos%?d\\t%0, %1"
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;[(set_attr "type" "float_em")])
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;
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;(define_insn "cosxf2"
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; [(set (match_operand:XF 0 "s_register_operand" "=f")
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; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 1))]
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; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")]
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; UNSEPC_COS))]
|
||||
; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
|
||||
; "cos%?e\\t%0, %1"
|
||||
;[(set_attr "type" "float_em")])
|
||||
|
|
@ -4119,7 +4162,7 @@
|
|||
|
||||
(define_insn "pic_load_addr_arm"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(unspec:SI [(match_operand:SI 1 "" "mX")] 3))]
|
||||
(unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
|
||||
"TARGET_ARM && flag_pic"
|
||||
"ldr%?\\t%0, %1"
|
||||
[(set_attr "type" "load")
|
||||
|
|
@ -4129,7 +4172,7 @@
|
|||
|
||||
(define_insn "pic_load_addr_thumb"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=l")
|
||||
(unspec:SI [(match_operand:SI 1 "" "mX")] 3))]
|
||||
(unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
|
||||
"TARGET_THUMB && flag_pic"
|
||||
"ldr\\t%0, %1"
|
||||
[(set_attr "type" "load")
|
||||
|
|
@ -4140,7 +4183,7 @@
|
|||
;; pic register in the rtl.
|
||||
(define_expand "pic_load_addr_based"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(unspec:SI [(match_operand 1 "" "") (match_dup 2)] 3))]
|
||||
(unspec:SI [(match_operand 1 "" "") (match_dup 2)] UNSPEC_PIC_SYM))]
|
||||
"TARGET_ARM && flag_pic"
|
||||
"operands[2] = pic_offset_table_rtx;"
|
||||
)
|
||||
|
|
@ -4148,7 +4191,8 @@
|
|||
(define_insn "*pic_load_addr_based_insn"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(unspec:SI [(match_operand 1 "" "")
|
||||
(match_operand 2 "s_register_operand" "r")] 3))]
|
||||
(match_operand 2 "s_register_operand" "r")]
|
||||
UNSPEC_PIC_SYM))]
|
||||
"TARGET_EITHER && flag_pic && operands[2] == pic_offset_table_rtx"
|
||||
"*
|
||||
#ifdef AOF_ASSEMBLER
|
||||
|
|
@ -6671,7 +6715,7 @@
|
|||
;; all of memory. This blocks insns from being moved across this point.
|
||||
|
||||
(define_insn "blockage"
|
||||
[(unspec_volatile [(const_int 0)] 0)]
|
||||
[(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
|
||||
"TARGET_EITHER"
|
||||
""
|
||||
[(set_attr "length" "0")
|
||||
|
|
@ -8600,7 +8644,7 @@
|
|||
)
|
||||
|
||||
(define_expand "epilogue"
|
||||
[(unspec_volatile [(return)] 1)]
|
||||
[(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
|
||||
"TARGET_EITHER"
|
||||
"
|
||||
if (TARGET_THUMB)
|
||||
|
|
@ -8613,13 +8657,13 @@
|
|||
emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
|
||||
gen_rtvec (1,
|
||||
gen_rtx_RETURN (VOIDmode)),
|
||||
1));
|
||||
VUNSPEC_EPILOGUE));
|
||||
DONE;
|
||||
"
|
||||
)
|
||||
|
||||
(define_insn "sibcall_epilogue"
|
||||
[(unspec_volatile [(const_int 0)] 1)]
|
||||
[(unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)]
|
||||
"TARGET_ARM"
|
||||
"*
|
||||
output_asm_insn (\"%@ Sibcall epilogue\", operands);
|
||||
|
|
@ -8633,7 +8677,7 @@
|
|||
)
|
||||
|
||||
(define_insn "*epilogue_insns"
|
||||
[(unspec_volatile [(return)] 1)]
|
||||
[(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
|
||||
"TARGET_EITHER"
|
||||
"*
|
||||
if (TARGET_ARM)
|
||||
|
|
@ -8838,7 +8882,8 @@
|
|||
(define_insn "*push_multi"
|
||||
[(match_parallel 2 "multi_register_push"
|
||||
[(set (match_operand:BLK 0 "memory_operand" "=m")
|
||||
(unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] 2))])]
|
||||
(unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")]
|
||||
UNSPEC_PUSH_MULT))])]
|
||||
"TARGET_ARM"
|
||||
"*
|
||||
{
|
||||
|
|
@ -8875,7 +8920,8 @@
|
|||
(define_insn "*push_fp_multi"
|
||||
[(match_parallel 2 "multi_register_push"
|
||||
[(set (match_operand:BLK 0 "memory_operand" "=m")
|
||||
(unspec:BLK [(match_operand:XF 1 "f_register_operand" "f")] 2))])]
|
||||
(unspec:BLK [(match_operand:XF 1 "f_register_operand" "f")]
|
||||
UNSPEC_PUSH_MULT))])]
|
||||
"TARGET_ARM"
|
||||
"*
|
||||
{
|
||||
|
|
@ -8891,7 +8937,7 @@
|
|||
;; Special patterns for dealing with the constant pool
|
||||
|
||||
(define_insn "align_4"
|
||||
[(unspec_volatile [(const_int 0)] 2)]
|
||||
[(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
|
||||
"TARGET_EITHER"
|
||||
"*
|
||||
assemble_align (32);
|
||||
|
|
@ -8900,7 +8946,7 @@
|
|||
)
|
||||
|
||||
(define_insn "consttable_end"
|
||||
[(unspec_volatile [(const_int 0)] 3)]
|
||||
[(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
|
||||
"TARGET_EITHER"
|
||||
"*
|
||||
making_const_table = FALSE;
|
||||
|
|
@ -8909,7 +8955,7 @@
|
|||
)
|
||||
|
||||
(define_insn "consttable_1"
|
||||
[(unspec_volatile [(match_operand 0 "" "")] 4)]
|
||||
[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)]
|
||||
"TARGET_THUMB"
|
||||
"*
|
||||
making_const_table = TRUE;
|
||||
|
|
@ -8921,7 +8967,7 @@
|
|||
)
|
||||
|
||||
(define_insn "consttable_2"
|
||||
[(unspec_volatile [(match_operand 0 "" "")] 5)]
|
||||
[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)]
|
||||
"TARGET_THUMB"
|
||||
"*
|
||||
making_const_table = TRUE;
|
||||
|
|
@ -8933,7 +8979,7 @@
|
|||
)
|
||||
|
||||
(define_insn "consttable_4"
|
||||
[(unspec_volatile [(match_operand 0 "" "")] 6)]
|
||||
[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
|
||||
"TARGET_EITHER"
|
||||
"*
|
||||
{
|
||||
|
|
@ -8957,7 +9003,7 @@
|
|||
)
|
||||
|
||||
(define_insn "consttable_8"
|
||||
[(unspec_volatile [(match_operand 0 "" "")] 7)]
|
||||
[(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
|
||||
"TARGET_EITHER"
|
||||
"*
|
||||
{
|
||||
|
|
@ -8994,16 +9040,37 @@
|
|||
|
||||
(define_insn "clz"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] 128))]
|
||||
"TARGET_ARM"
|
||||
(unspec:SI [(match_operand:SI 1 "s_register_operand" "r")]
|
||||
UNSPEC_CLZ))]
|
||||
"TARGET_ARM && arm_arch5"
|
||||
"clz\\t%0, %1")
|
||||
|
||||
;; XScale instructions.
|
||||
(define_expand "ffssi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(ffs:SI (match_operand:SI 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && arm_arch5"
|
||||
"
|
||||
{
|
||||
rtx t1, t2, t3;
|
||||
|
||||
t1 = gen_reg_rtx (SImode);
|
||||
t2 = gen_reg_rtx (SImode);
|
||||
t3 = gen_reg_rtx (SImode);
|
||||
|
||||
emit_insn (gen_negsi2 (t1, operands[1]));
|
||||
emit_insn (gen_andsi3 (t2, operands[1], t1));
|
||||
emit_insn (gen_clz (t3, t2));
|
||||
emit_insn (gen_subsi3 (operands[0], GEN_INT (32), t3));
|
||||
DONE;
|
||||
}"
|
||||
)
|
||||
|
||||
;; V5E instructions.
|
||||
|
||||
(define_insn "prefetch"
|
||||
[(unspec_volatile
|
||||
[(match_operand:SI 0 "offsettable_memory_operand" "o")] 129)]
|
||||
"TARGET_ARM"
|
||||
[(match_operand:SI 0 "offsettable_memory_operand" "o")] VUNSPEC_PREFETCH)]
|
||||
"TARGET_ARM && arm_arch5e"
|
||||
"pld\\t%0")
|
||||
|
||||
;; General predication pattern
|
||||
|
|
|
|||
Loading…
Reference in New Issue