[AArch64 costs 10/18] Improve costs for sign/zero extend operations
gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost ZERO_EXTEND and SIGN_EXTEND better. Co-Authored-By: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> From-SVN: r210502
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@ -1,3 +1,9 @@
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2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
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Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost
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ZERO_EXTEND and SIGN_EXTEND better.
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2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
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Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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@ -5281,21 +5281,62 @@ cost_minus:
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return false;
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case ZERO_EXTEND:
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if ((GET_MODE (x) == DImode
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&& GET_MODE (XEXP (x, 0)) == SImode)
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|| GET_CODE (XEXP (x, 0)) == MEM)
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op0 = XEXP (x, 0);
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/* If a value is written in SI mode, then zero extended to DI
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mode, the operation will in general be free as a write to
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a 'w' register implicitly zeroes the upper bits of an 'x'
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register. However, if this is
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(set (reg) (zero_extend (reg)))
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we must cost the explicit register move. */
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if (mode == DImode
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&& GET_MODE (op0) == SImode
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&& outer == SET)
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{
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*cost += rtx_cost (XEXP (x, 0), ZERO_EXTEND, 0, speed);
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int op_cost = rtx_cost (XEXP (x, 0), ZERO_EXTEND, 0, speed);
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if (!op_cost && speed)
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/* MOV. */
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*cost += extra_cost->alu.extend;
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else
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/* Free, the cost is that of the SI mode operation. */
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*cost = op_cost;
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return true;
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}
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else if (MEM_P (XEXP (x, 0)))
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{
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/* All loads can zero extend to any size for free. */
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*cost = rtx_cost (XEXP (x, 0), ZERO_EXTEND, param, speed);
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return true;
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}
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/* UXTB/UXTH. */
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if (speed)
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*cost += extra_cost->alu.extend;
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return false;
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case SIGN_EXTEND:
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if (GET_CODE (XEXP (x, 0)) == MEM)
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if (MEM_P (XEXP (x, 0)))
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{
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*cost += rtx_cost (XEXP (x, 0), SIGN_EXTEND, 0, speed);
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/* LDRSH. */
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if (speed)
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{
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rtx address = XEXP (XEXP (x, 0), 0);
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*cost += extra_cost->ldst.load_sign_extend;
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*cost +=
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COSTS_N_INSNS (aarch64_address_cost (address, mode,
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0, speed));
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}
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return true;
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}
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if (speed)
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*cost += extra_cost->alu.extend;
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return false;
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case ROTATE:
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