timevar.def (TV_SCHED_FUSION): New time var.
* timevar.def (TV_SCHED_FUSION): New time var. * passes.def (pass_sched_fusion): New pass. * config/arm/arm.c (TARGET_SCHED_FUSION_PRIORITY): New. (extract_base_offset_in_addr, fusion_load_store): New. (arm_sched_fusion_priority): New. (arm_option_override): Disable scheduling fusion by default on non-armv7 processors or ldrd/strd isn't preferred. * sched-int.h (struct _haifa_insn_data): New field. (INSN_FUSION_PRIORITY, FUSION_MAX_PRIORITY, sched_fusion): New. * sched-rgn.c (rest_of_handle_sched_fusion): New. (pass_data_sched_fusion, pass_sched_fusion): New. (make_pass_sched_fusion): New. * haifa-sched.c (sched_fusion): New. (insn_cost): Handle sched_fusion. (priority): Handle sched_fusion by calling target hook. (enum rfs_decision): New enum value. (rfs_str): New element for RFS_FUSION. (rank_for_schedule): Support sched_fusion. (schedule_insn, max_issue, prune_ready_list): Handle sched_fusion. (schedule_block, fix_tick_ready): Handle sched_fusion. * common.opt (flag_schedule_fusion): New. * tree-pass.h (make_pass_sched_fusion): New. * target.def (fusion_priority): New. * doc/tm.texi.in (TARGET_SCHED_FUSION_PRIORITY): New. * doc/tm.texi: Regenerated. * doc/invoke.texi (-fschedule-fusion): New. testsuite: * gcc.target/arm/ldrd-strd-pair-1.c: New test. * gcc.target/arm/vfp-1.c: Improve scanning string. From-SVN: r217533
This commit is contained in:
Bin Cheng
Bin Cheng
parent
0fb3402f69
commit
b16abbcb85
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@ -1,3 +1,32 @@
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2014-11-14 Bin Cheng <bin.cheng@arm.com>
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* timevar.def (TV_SCHED_FUSION): New time var.
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* passes.def (pass_sched_fusion): New pass.
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* config/arm/arm.c (TARGET_SCHED_FUSION_PRIORITY): New.
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(extract_base_offset_in_addr, fusion_load_store): New.
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(arm_sched_fusion_priority): New.
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(arm_option_override): Disable scheduling fusion by default
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on non-armv7 processors or ldrd/strd isn't preferred.
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* sched-int.h (struct _haifa_insn_data): New field.
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(INSN_FUSION_PRIORITY, FUSION_MAX_PRIORITY, sched_fusion): New.
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* sched-rgn.c (rest_of_handle_sched_fusion): New.
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(pass_data_sched_fusion, pass_sched_fusion): New.
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(make_pass_sched_fusion): New.
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* haifa-sched.c (sched_fusion): New.
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(insn_cost): Handle sched_fusion.
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(priority): Handle sched_fusion by calling target hook.
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(enum rfs_decision): New enum value.
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(rfs_str): New element for RFS_FUSION.
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(rank_for_schedule): Support sched_fusion.
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(schedule_insn, max_issue, prune_ready_list): Handle sched_fusion.
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(schedule_block, fix_tick_ready): Handle sched_fusion.
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* common.opt (flag_schedule_fusion): New.
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* tree-pass.h (make_pass_sched_fusion): New.
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* target.def (fusion_priority): New.
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* doc/tm.texi.in (TARGET_SCHED_FUSION_PRIORITY): New.
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* doc/tm.texi: Regenerated.
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* doc/invoke.texi (-fschedule-fusion): New.
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2014-11-13 Rong Xu <xur@google.com>
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PR debug/63581
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@ -1848,6 +1848,10 @@ frename-registers
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Common Report Var(flag_rename_registers) Init(2) Optimization
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Perform a register renaming optimization pass
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fschedule-fusion
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Common Report Var(flag_schedule_fusion) Init(2) Optimization
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Perform a target dependent instruction fusion optimization pass
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freorder-blocks
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Common Report Var(flag_reorder_blocks) Optimization
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Reorder basic blocks to improve code placement
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@ -311,6 +311,8 @@ static unsigned arm_add_stmt_cost (void *data, int count,
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static void arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
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bool op0_preserve_value);
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static unsigned HOST_WIDE_INT arm_asan_shadow_offset (void);
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static void arm_sched_fusion_priority (rtx_insn *, int, int *, int*);
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/* Table of machine attributes. */
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static const struct attribute_spec arm_attribute_table[] =
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@ -708,6 +710,9 @@ static const struct attribute_spec arm_attribute_table[] =
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#undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
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#define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
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#undef TARGET_SCHED_FUSION_PRIORITY
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#define TARGET_SCHED_FUSION_PRIORITY arm_sched_fusion_priority
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Obstack for minipool constant handling. */
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@ -3168,6 +3173,12 @@ arm_option_override (void)
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if (TARGET_THUMB2)
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inline_asm_unified = 1;
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/* Disable scheduling fusion by default if it's not armv7 processor
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or doesn't prefer ldrd/strd. */
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if (flag_schedule_fusion == 2
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&& (!arm_arch7 || !current_tune->prefer_ldrd_strd))
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flag_schedule_fusion = 0;
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/* Register global variables with the garbage collector. */
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arm_add_gc_roots ();
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}
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@ -32350,4 +32361,124 @@ arm_is_constant_pool_ref (rtx x)
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&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
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}
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/* If MEM is in the form of [base+offset], extract the two parts
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of address and set to BASE and OFFSET, otherwise return false
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after clearing BASE and OFFSET. */
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static bool
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extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
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{
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rtx addr;
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gcc_assert (MEM_P (mem));
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addr = XEXP (mem, 0);
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/* Strip off const from addresses like (const (addr)). */
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if (GET_CODE (addr) == CONST)
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addr = XEXP (addr, 0);
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if (GET_CODE (addr) == REG)
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{
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*base = addr;
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*offset = const0_rtx;
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return true;
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}
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if (GET_CODE (addr) == PLUS
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&& GET_CODE (XEXP (addr, 0)) == REG
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&& CONST_INT_P (XEXP (addr, 1)))
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{
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*base = XEXP (addr, 0);
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*offset = XEXP (addr, 1);
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return true;
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}
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*base = NULL_RTX;
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*offset = NULL_RTX;
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return false;
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}
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/* If INSN is a load or store of address in the form of [base+offset],
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extract the two parts and set to BASE and OFFSET. IS_LOAD is set
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to TRUE if it's a load. Return TRUE if INSN is such an instruction,
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otherwise return FALSE. */
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static bool
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fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset, bool *is_load)
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{
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rtx x, dest, src;
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gcc_assert (INSN_P (insn));
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x = PATTERN (insn);
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if (GET_CODE (x) != SET)
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return false;
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src = SET_SRC (x);
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dest = SET_DEST (x);
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if (GET_CODE (src) == REG && GET_CODE (dest) == MEM)
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{
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*is_load = false;
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extract_base_offset_in_addr (dest, base, offset);
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}
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else if (GET_CODE (src) == MEM && GET_CODE (dest) == REG)
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{
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*is_load = true;
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extract_base_offset_in_addr (src, base, offset);
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}
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else
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return false;
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return (*base != NULL_RTX && *offset != NULL_RTX);
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}
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/* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
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Currently we only support to fuse ldr or str instructions, so FUSION_PRI
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and PRI are only calculated for these instructions. For other instruction,
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FUSION_PRI and PRI are simply set to MAX_PRI. In the future, other kind
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instruction fusion can be supported by returning different priorities.
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It's important that irrelevant instructions get the largest FUSION_PRI. */
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static void
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arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
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int *fusion_pri, int *pri)
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{
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int tmp, off_val;
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bool is_load;
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rtx base, offset;
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gcc_assert (INSN_P (insn));
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tmp = max_pri - 1;
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if (!fusion_load_store (insn, &base, &offset, &is_load))
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{
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*pri = tmp;
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*fusion_pri = tmp;
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return;
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}
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/* Load goes first. */
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if (is_load)
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*fusion_pri = tmp - 1;
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else
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*fusion_pri = tmp - 2;
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tmp /= 2;
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/* INSN with smaller base register goes first. */
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tmp -= ((REGNO (base) & 0xff) << 20);
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/* INSN with smaller offset goes first. */
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off_val = (int)(INTVAL (offset));
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if (off_val >= 0)
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tmp -= (off_val & 0xfffff);
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else
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tmp += ((- off_val) & 0xfffff);
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*pri = tmp;
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return;
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}
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#include "gt-arm.h"
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@ -406,7 +406,7 @@ Objective-C and Objective-C++ Dialects}.
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-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol
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-fprofile-generate=@var{path} @gol
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-fprofile-use -fprofile-use=@var{path} -fprofile-values -fprofile-reorder-functions @gol
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-freciprocal-math -free -frename-registers -freorder-blocks @gol
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-freciprocal-math -free -frename-registers -fschedule-fusion -freorder-blocks @gol
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-freorder-blocks-and-partition -freorder-functions @gol
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-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol
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-frounding-math -fsched2-use-superblocks -fsched-pressure @gol
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@ -9575,6 +9575,14 @@ a ``home register''.
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Enabled by default with @option{-funroll-loops} and @option{-fpeel-loops}.
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@item -fschedule-fusion
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@opindex fschedule-fusion
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Performs a target dependent pass over the instruction stream to schedule
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instructions of same type together because target machine can execute them
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more efficiently if they are adjacent to each other in the instruction flow.
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Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
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@item -ftracer
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@opindex ftracer
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Perform tail duplication to enlarge superblock size. This transformation
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@ -6771,6 +6771,76 @@ This hook is called by tree reassociator to determine a level of
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parallelism required in output calculations chain.
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@end deftypefn
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@deftypefn {Target Hook} void TARGET_SCHED_FUSION_PRIORITY (rtx_insn *@var{insn}, int @var{max_pri}, int *@var{fusion_pri}, int *@var{pri})
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This hook is called by scheduling fusion pass. It calculates fusion
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priorities for each instruction passed in by parameter. The priorities
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are returned via pointer parameters.
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@var{insn} is the instruction whose priorities need to be calculated.
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@var{max_pri} is the maximum priority can be returned in any cases.
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@var{fusion_pri} is the pointer parameter through which @var{insn}'s
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fusion priority should be calculated and returned.
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@var{pri} is the pointer parameter through which @var{insn}'s priority
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should be calculated and returned.
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Same @var{fusion_pri} should be returned for instructions which should
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be scheduled together. Different @var{pri} should be returned for
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instructions with same @var{fusion_pri}. @var{fusion_pri} is the major
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sort key, @var{pri} is the minor sort key. All instructions will be
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scheduled according to the two priorities. All priorities calculated
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should be between 0 (exclusive) and @var{max_pri} (inclusive). To avoid
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false dependencies, @var{fusion_pri} of instructions which need to be
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scheduled together should be smaller than @var{fusion_pri} of irrelevant
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instructions.
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Given below example:
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ldr r10, [r1, 4]
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add r4, r4, r10
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ldr r15, [r2, 8]
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sub r5, r5, r15
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ldr r11, [r1, 0]
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add r4, r4, r11
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ldr r16, [r2, 12]
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sub r5, r5, r16
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On targets like ARM/AArch64, the two pairs of consecutive loads should be
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merged. Since peephole2 pass can't help in this case unless consecutive
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loads are actually next to each other in instruction flow. That's where
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this scheduling fusion pass works. This hook calculates priority for each
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instruction based on its fustion type, like:
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ldr r10, [r1, 4] ; fusion_pri=99, pri=96
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add r4, r4, r10 ; fusion_pri=100, pri=100
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ldr r15, [r2, 8] ; fusion_pri=98, pri=92
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sub r5, r5, r15 ; fusion_pri=100, pri=100
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ldr r11, [r1, 0] ; fusion_pri=99, pri=100
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add r4, r4, r11 ; fusion_pri=100, pri=100
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ldr r16, [r2, 12] ; fusion_pri=98, pri=88
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sub r5, r5, r16 ; fusion_pri=100, pri=100
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Scheduling fusion pass then sorts all ready to issue instructions according
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to the priorities. As a result, instructions of same fusion type will be
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pushed together in instruction flow, like:
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ldr r11, [r1, 0]
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ldr r10, [r1, 4]
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ldr r15, [r2, 8]
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ldr r16, [r2, 12]
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add r4, r4, r10
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sub r5, r5, r15
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add r4, r4, r11
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sub r5, r5, r16
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Now peephole2 pass can simply merge the two pairs of loads.
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Since scheduling fusion pass relies on peephole2 to do real fusion
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work, it is only enabled by default when peephole2 is in effect.
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This is firstly introduced on ARM/AArch64 targets, please refer to
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the hook implementation for how different fusion types are supported.
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@end deftypefn
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@node Sections
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@section Dividing the Output into Sections (Texts, Data, @dots{})
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@c the above section title is WAY too long. maybe cut the part between
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@ -4811,6 +4811,8 @@ them: try the first ones in this list first.
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@hook TARGET_SCHED_REASSOCIATION_WIDTH
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@hook TARGET_SCHED_FUSION_PRIORITY
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@node Sections
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@section Dividing the Output into Sections (Texts, Data, @dots{})
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@c the above section title is WAY too long. maybe cut the part between
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|
|
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@ -1391,6 +1391,9 @@ insn_cost (rtx_insn *insn)
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{
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int cost;
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if (sched_fusion)
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return 0;
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if (sel_sched_p ())
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{
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if (recog_memoized (insn) < 0)
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@ -1603,6 +1606,8 @@ dep_list_size (rtx insn, sd_list_types_def list)
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return nodbgcount;
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}
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bool sched_fusion;
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/* Compute the priority number for INSN. */
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static int
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priority (rtx_insn *insn)
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@ -1617,7 +1622,15 @@ priority (rtx_insn *insn)
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{
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int this_priority = -1;
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if (dep_list_size (insn, SD_LIST_FORW) == 0)
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if (sched_fusion)
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{
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int this_fusion_priority;
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targetm.sched.fusion_priority (insn, FUSION_MAX_PRIORITY,
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&this_fusion_priority, &this_priority);
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INSN_FUSION_PRIORITY (insn) = this_fusion_priority;
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}
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else if (dep_list_size (insn, SD_LIST_FORW) == 0)
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/* ??? We should set INSN_PRIORITY to insn_cost when and insn has
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some forward deps but all of them are ignored by
|
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contributes_to_priority hook. At the moment we set priority of
|
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|
|
@ -2548,7 +2561,7 @@ enum rfs_decision {
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RFS_SCHED_GROUP, RFS_PRESSURE_DELAY, RFS_PRESSURE_TICK,
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RFS_FEEDS_BACKTRACK_INSN, RFS_PRIORITY, RFS_SPECULATION,
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RFS_SCHED_RANK, RFS_LAST_INSN, RFS_PRESSURE_INDEX,
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RFS_DEP_COUNT, RFS_TIE, RFS_N };
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RFS_DEP_COUNT, RFS_TIE, RFS_FUSION, RFS_N };
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|
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/* Corresponding strings for print outs. */
|
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static const char *rfs_str[RFS_N] = {
|
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|
|
@ -2556,7 +2569,7 @@ static const char *rfs_str[RFS_N] = {
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"RFS_SCHED_GROUP", "RFS_PRESSURE_DELAY", "RFS_PRESSURE_TICK",
|
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"RFS_FEEDS_BACKTRACK_INSN", "RFS_PRIORITY", "RFS_SPECULATION",
|
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"RFS_SCHED_RANK", "RFS_LAST_INSN", "RFS_PRESSURE_INDEX",
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"RFS_DEP_COUNT", "RFS_TIE" };
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"RFS_DEP_COUNT", "RFS_TIE", "RFS_FUSION" };
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/* Statistical breakdown of rank_for_schedule decisions. */
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typedef struct { unsigned stats[RFS_N]; } rank_for_schedule_stats_t;
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|
|
@ -2627,6 +2640,55 @@ rank_for_schedule (const void *x, const void *y)
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/* Make sure that priority of TMP and TMP2 are initialized. */
|
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gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
|
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|
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if (sched_fusion)
|
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{
|
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/* The instruction that has the same fusion priority as the last
|
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instruction is the instruction we picked next. If that is not
|
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the case, we sort ready list firstly by fusion priority, then
|
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by priority, and at last by INSN_LUID. */
|
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int a = INSN_FUSION_PRIORITY (tmp);
|
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int b = INSN_FUSION_PRIORITY (tmp2);
|
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int last = -1;
|
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|
||||
if (last_nondebug_scheduled_insn
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&& !NOTE_P (last_nondebug_scheduled_insn)
|
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&& BLOCK_FOR_INSN (tmp)
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== BLOCK_FOR_INSN (last_nondebug_scheduled_insn))
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last = INSN_FUSION_PRIORITY (last_nondebug_scheduled_insn);
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|
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if (a != last && b != last)
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{
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if (a == b)
|
||||
{
|
||||
a = INSN_PRIORITY (tmp);
|
||||
b = INSN_PRIORITY (tmp2);
|
||||
}
|
||||
if (a != b)
|
||||
return rfs_result (RFS_FUSION, b - a, tmp, tmp2);
|
||||
else
|
||||
return rfs_result (RFS_FUSION,
|
||||
INSN_LUID (tmp) - INSN_LUID (tmp2), tmp, tmp2);
|
||||
}
|
||||
else if (a == b)
|
||||
{
|
||||
gcc_assert (last_nondebug_scheduled_insn
|
||||
&& !NOTE_P (last_nondebug_scheduled_insn));
|
||||
last = INSN_PRIORITY (last_nondebug_scheduled_insn);
|
||||
|
||||
a = abs (INSN_PRIORITY (tmp) - last);
|
||||
b = abs (INSN_PRIORITY (tmp2) - last);
|
||||
if (a != b)
|
||||
return rfs_result (RFS_FUSION, a - b, tmp, tmp2);
|
||||
else
|
||||
return rfs_result (RFS_FUSION,
|
||||
INSN_LUID (tmp) - INSN_LUID (tmp2), tmp, tmp2);
|
||||
}
|
||||
else if (a == last)
|
||||
return rfs_result (RFS_FUSION, -1, tmp, tmp2);
|
||||
else
|
||||
return rfs_result (RFS_FUSION, 1, tmp, tmp2);
|
||||
}
|
||||
|
||||
if (sched_pressure != SCHED_PRESSURE_NONE)
|
||||
{
|
||||
/* Prefer insn whose scheduling results in the smallest register
|
||||
|
|
@ -4007,8 +4069,8 @@ schedule_insn (rtx_insn *insn)
|
|||
gcc_assert (INSN_TICK (insn) >= MIN_TICK);
|
||||
if (INSN_TICK (insn) > clock_var)
|
||||
/* INSN has been prematurely moved from the queue to the ready list.
|
||||
This is possible only if following flag is set. */
|
||||
gcc_assert (flag_sched_stalled_insns);
|
||||
This is possible only if following flags are set. */
|
||||
gcc_assert (flag_sched_stalled_insns || sched_fusion);
|
||||
|
||||
/* ??? Probably, if INSN is scheduled prematurely, we should leave
|
||||
INSN_TICK untouched. This is a machine-dependent issue, actually. */
|
||||
|
|
@ -5500,6 +5562,9 @@ max_issue (struct ready_list *ready, int privileged_n, state_t state,
|
|||
struct choice_entry *top;
|
||||
rtx_insn *insn;
|
||||
|
||||
if (sched_fusion)
|
||||
return 0;
|
||||
|
||||
n_ready = ready->n_ready;
|
||||
gcc_assert (dfa_lookahead >= 1 && privileged_n >= 0
|
||||
&& privileged_n <= n_ready);
|
||||
|
|
@ -5848,6 +5913,9 @@ prune_ready_list (state_t temp_state, bool first_cycle_insn_p,
|
|||
bool sched_group_found = false;
|
||||
int min_cost_group = 1;
|
||||
|
||||
if (sched_fusion)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ready.n_ready; i++)
|
||||
{
|
||||
rtx_insn *insn = ready_element (&ready, i);
|
||||
|
|
@ -6059,7 +6127,7 @@ schedule_block (basic_block *target_bb, state_t init_state)
|
|||
rtx_insn *tail = PREV_INSN (next_tail);
|
||||
|
||||
if ((current_sched_info->flags & DONT_BREAK_DEPENDENCIES) == 0
|
||||
&& sched_pressure != SCHED_PRESSURE_MODEL)
|
||||
&& sched_pressure != SCHED_PRESSURE_MODEL && !sched_fusion)
|
||||
find_modifiable_mems (head, tail);
|
||||
|
||||
/* We used to have code to avoid getting parameters moved from hard
|
||||
|
|
@ -6455,7 +6523,7 @@ schedule_block (basic_block *target_bb, state_t init_state)
|
|||
{
|
||||
memcpy (temp_state, curr_state, dfa_state_size);
|
||||
cost = state_transition (curr_state, insn);
|
||||
if (sched_pressure != SCHED_PRESSURE_WEIGHTED)
|
||||
if (sched_pressure != SCHED_PRESSURE_WEIGHTED && !sched_fusion)
|
||||
gcc_assert (cost < 0);
|
||||
if (memcmp (temp_state, curr_state, dfa_state_size) != 0)
|
||||
cycle_issued_insns++;
|
||||
|
|
@ -7288,7 +7356,7 @@ fix_tick_ready (rtx_insn *next)
|
|||
INSN_TICK (next) = tick;
|
||||
|
||||
delay = tick - clock_var;
|
||||
if (delay <= 0 || sched_pressure != SCHED_PRESSURE_NONE)
|
||||
if (delay <= 0 || sched_pressure != SCHED_PRESSURE_NONE || sched_fusion)
|
||||
delay = QUEUE_READY;
|
||||
|
||||
change_queue_index (next, delay);
|
||||
|
|
|
|||
|
|
@ -419,6 +419,7 @@ along with GCC; see the file COPYING3. If not see
|
|||
NEXT_PASS (pass_stack_adjustments);
|
||||
NEXT_PASS (pass_jump2);
|
||||
NEXT_PASS (pass_duplicate_computed_gotos);
|
||||
NEXT_PASS (pass_sched_fusion);
|
||||
NEXT_PASS (pass_peephole2);
|
||||
NEXT_PASS (pass_if_after_reload);
|
||||
NEXT_PASS (pass_regrename);
|
||||
|
|
|
|||
|
|
@ -805,6 +805,9 @@ struct _haifa_insn_data
|
|||
/* A priority for each insn. */
|
||||
int priority;
|
||||
|
||||
/* The fusion priority for each insn. */
|
||||
int fusion_priority;
|
||||
|
||||
/* The minimum clock tick at which the insn becomes ready. This is
|
||||
used to note timing constraints for the insns in the pending list. */
|
||||
int tick;
|
||||
|
|
@ -903,6 +906,7 @@ extern vec<haifa_insn_data_def> h_i_d;
|
|||
/* Accessor macros for h_i_d. There are more in haifa-sched.c and
|
||||
sched-rgn.c. */
|
||||
#define INSN_PRIORITY(INSN) (HID (INSN)->priority)
|
||||
#define INSN_FUSION_PRIORITY(INSN) (HID (INSN)->fusion_priority)
|
||||
#define INSN_REG_PRESSURE(INSN) (HID (INSN)->reg_pressure)
|
||||
#define INSN_MAX_REG_PRESSURE(INSN) (HID (INSN)->max_reg_pressure)
|
||||
#define INSN_REG_USE_LIST(INSN) (HID (INSN)->reg_use_list)
|
||||
|
|
@ -1620,6 +1624,10 @@ extern void sd_copy_back_deps (rtx_insn *, rtx_insn *, bool);
|
|||
extern void sd_delete_dep (sd_iterator_def);
|
||||
extern void sd_debug_lists (rtx, sd_list_types_def);
|
||||
|
||||
/* Macros and declarations for scheduling fusion. */
|
||||
#define FUSION_MAX_PRIORITY (INT_MAX)
|
||||
extern bool sched_fusion;
|
||||
|
||||
#endif /* INSN_SCHEDULING */
|
||||
|
||||
#endif /* GCC_SCHED_INT_H */
|
||||
|
|
|
|||
|
|
@ -3658,6 +3658,17 @@ rest_of_handle_sched2 (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
rest_of_handle_sched_fusion (void)
|
||||
{
|
||||
#ifdef INSN_SCHEDULING
|
||||
sched_fusion = true;
|
||||
schedule_insns ();
|
||||
sched_fusion = false;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
const pass_data pass_data_live_range_shrinkage =
|
||||
|
|
@ -3800,3 +3811,55 @@ make_pass_sched2 (gcc::context *ctxt)
|
|||
{
|
||||
return new pass_sched2 (ctxt);
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
const pass_data pass_data_sched_fusion =
|
||||
{
|
||||
RTL_PASS, /* type */
|
||||
"sched_fusion", /* name */
|
||||
OPTGROUP_NONE, /* optinfo_flags */
|
||||
TV_SCHED_FUSION, /* tv_id */
|
||||
0, /* properties_required */
|
||||
0, /* properties_provided */
|
||||
0, /* properties_destroyed */
|
||||
0, /* todo_flags_start */
|
||||
TODO_df_finish, /* todo_flags_finish */
|
||||
};
|
||||
|
||||
class pass_sched_fusion : public rtl_opt_pass
|
||||
{
|
||||
public:
|
||||
pass_sched_fusion (gcc::context *ctxt)
|
||||
: rtl_opt_pass (pass_data_sched_fusion, ctxt)
|
||||
{}
|
||||
|
||||
/* opt_pass methods: */
|
||||
virtual bool gate (function *);
|
||||
virtual unsigned int execute (function *)
|
||||
{
|
||||
return rest_of_handle_sched_fusion ();
|
||||
}
|
||||
|
||||
}; // class pass_sched2
|
||||
|
||||
bool
|
||||
pass_sched_fusion::gate (function *)
|
||||
{
|
||||
#ifdef INSN_SCHEDULING
|
||||
/* Scheduling fusion relies on peephole2 to do real fusion work,
|
||||
so only enable it if peephole2 is in effect. */
|
||||
return (optimize > 0 && flag_peephole2
|
||||
&& flag_schedule_fusion && targetm.sched.fusion_priority != NULL);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
} // anon namespace
|
||||
|
||||
rtl_opt_pass *
|
||||
make_pass_sched_fusion (gcc::context *ctxt)
|
||||
{
|
||||
return new pass_sched_fusion (ctxt);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1526,6 +1526,79 @@ parallelism required in output calculations chain.",
|
|||
int, (unsigned int opc, machine_mode mode),
|
||||
hook_int_uint_mode_1)
|
||||
|
||||
/* The following member value is a function that returns priority for
|
||||
fusion of each instruction via pointer parameters. */
|
||||
DEFHOOK
|
||||
(fusion_priority,
|
||||
"This hook is called by scheduling fusion pass. It calculates fusion\n\
|
||||
priorities for each instruction passed in by parameter. The priorities\n\
|
||||
are returned via pointer parameters.\n\
|
||||
\n\
|
||||
@var{insn} is the instruction whose priorities need to be calculated.\n\
|
||||
@var{max_pri} is the maximum priority can be returned in any cases.\n\
|
||||
@var{fusion_pri} is the pointer parameter through which @var{insn}'s\n\
|
||||
fusion priority should be calculated and returned.\n\
|
||||
@var{pri} is the pointer parameter through which @var{insn}'s priority\n\
|
||||
should be calculated and returned.\n\
|
||||
\n\
|
||||
Same @var{fusion_pri} should be returned for instructions which should\n\
|
||||
be scheduled together. Different @var{pri} should be returned for\n\
|
||||
instructions with same @var{fusion_pri}. @var{fusion_pri} is the major\n\
|
||||
sort key, @var{pri} is the minor sort key. All instructions will be\n\
|
||||
scheduled according to the two priorities. All priorities calculated\n\
|
||||
should be between 0 (exclusive) and @var{max_pri} (inclusive). To avoid\n\
|
||||
false dependencies, @var{fusion_pri} of instructions which need to be\n\
|
||||
scheduled together should be smaller than @var{fusion_pri} of irrelevant\n\
|
||||
instructions.\n\
|
||||
\n\
|
||||
Given below example:\n\
|
||||
\n\
|
||||
ldr r10, [r1, 4]\n\
|
||||
add r4, r4, r10\n\
|
||||
ldr r15, [r2, 8]\n\
|
||||
sub r5, r5, r15\n\
|
||||
ldr r11, [r1, 0]\n\
|
||||
add r4, r4, r11\n\
|
||||
ldr r16, [r2, 12]\n\
|
||||
sub r5, r5, r16\n\
|
||||
\n\
|
||||
On targets like ARM/AArch64, the two pairs of consecutive loads should be\n\
|
||||
merged. Since peephole2 pass can't help in this case unless consecutive\n\
|
||||
loads are actually next to each other in instruction flow. That's where\n\
|
||||
this scheduling fusion pass works. This hook calculates priority for each\n\
|
||||
instruction based on its fustion type, like:\n\
|
||||
\n\
|
||||
ldr r10, [r1, 4] ; fusion_pri=99, pri=96 \n\
|
||||
add r4, r4, r10 ; fusion_pri=100, pri=100 \n\
|
||||
ldr r15, [r2, 8] ; fusion_pri=98, pri=92 \n\
|
||||
sub r5, r5, r15 ; fusion_pri=100, pri=100 \n\
|
||||
ldr r11, [r1, 0] ; fusion_pri=99, pri=100 \n\
|
||||
add r4, r4, r11 ; fusion_pri=100, pri=100 \n\
|
||||
ldr r16, [r2, 12] ; fusion_pri=98, pri=88 \n\
|
||||
sub r5, r5, r16 ; fusion_pri=100, pri=100 \n\
|
||||
\n\
|
||||
Scheduling fusion pass then sorts all ready to issue instructions according\n\
|
||||
to the priorities. As a result, instructions of same fusion type will be\n\
|
||||
pushed together in instruction flow, like:\n\
|
||||
\n\
|
||||
ldr r11, [r1, 0]\n\
|
||||
ldr r10, [r1, 4]\n\
|
||||
ldr r15, [r2, 8]\n\
|
||||
ldr r16, [r2, 12]\n\
|
||||
add r4, r4, r10\n\
|
||||
sub r5, r5, r15\n\
|
||||
add r4, r4, r11\n\
|
||||
sub r5, r5, r16\n\
|
||||
\n\
|
||||
Now peephole2 pass can simply merge the two pairs of loads.\n\
|
||||
\n\
|
||||
Since scheduling fusion pass relies on peephole2 to do real fusion\n\
|
||||
work, it is only enabled by default when peephole2 is in effect.\n\
|
||||
\n\
|
||||
This is firstly introduced on ARM/AArch64 targets, please refer to\n\
|
||||
the hook implementation for how different fusion types are supported.",
|
||||
void, (rtx_insn *insn, int max_pri, int *fusion_pri, int *pri), NULL)
|
||||
|
||||
HOOK_VECTOR_END (sched)
|
||||
|
||||
/* Functions relating to OpenMP and Cilk Plus SIMD clones. */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2014-11-14 Bin Cheng <bin.cheng@arm.com>
|
||||
|
||||
* gcc.target/arm/ldrd-strd-pair-1.c: New test.
|
||||
* gcc.target/arm/vfp-1.c: Improve scanning string.
|
||||
|
||||
2014-11-13 Rong Xu <xur@google.com>
|
||||
|
||||
PR debug/63581
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target arm_prefer_ldrd_strd } */
|
||||
/* { dg-options "-O2 -mthumb" } */
|
||||
|
||||
struct
|
||||
{
|
||||
int x;
|
||||
int y;
|
||||
char c;
|
||||
int d;
|
||||
}a;
|
||||
|
||||
int foo(int x, int y)
|
||||
{
|
||||
int c;
|
||||
a.x = x;
|
||||
c = a.x;
|
||||
a.d = c;
|
||||
a.y = y;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/* { dg-final { scan-assembler "strd\t" { target { arm_thumb2_ok } } } } */
|
||||
|
|
@ -126,7 +126,7 @@ void test_convert () {
|
|||
}
|
||||
|
||||
void test_ldst (float f[], double d[]) {
|
||||
/* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #1020\\\]" } } */
|
||||
/* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #-?\[0-9\]+\\\]" } } */
|
||||
/* { dg-final { scan-assembler "vldr.32.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
|
||||
/* { dg-final { scan-assembler "add.+ r0, #1024" } } */
|
||||
/* { dg-final { scan-assembler "vstr.32.+ \\\[r\[0-9\]\\\]\n" } } */
|
||||
|
|
|
|||
|
|
@ -247,6 +247,7 @@ DEFTIMEVAR (TV_IFCVT2 , "if-conversion 2")
|
|||
DEFTIMEVAR (TV_COMBINE_STACK_ADJUST , "combine stack adjustments")
|
||||
DEFTIMEVAR (TV_PEEPHOLE2 , "peephole 2")
|
||||
DEFTIMEVAR (TV_RENAME_REGISTERS , "rename registers")
|
||||
DEFTIMEVAR (TV_SCHED_FUSION , "scheduling fusion")
|
||||
DEFTIMEVAR (TV_CPROP_REGISTERS , "hard reg cprop")
|
||||
DEFTIMEVAR (TV_SCHED2 , "scheduling 2")
|
||||
DEFTIMEVAR (TV_MACH_DEP , "machine dep reorg")
|
||||
|
|
|
|||
|
|
@ -552,6 +552,7 @@ extern rtl_opt_pass *make_pass_branch_target_load_optimize1 (gcc::context
|
|||
extern rtl_opt_pass *make_pass_thread_prologue_and_epilogue (gcc::context
|
||||
*ctxt);
|
||||
extern rtl_opt_pass *make_pass_stack_adjustments (gcc::context *ctxt);
|
||||
extern rtl_opt_pass *make_pass_sched_fusion (gcc::context *ctxt);
|
||||
extern rtl_opt_pass *make_pass_peephole2 (gcc::context *ctxt);
|
||||
extern rtl_opt_pass *make_pass_if_after_reload (gcc::context *ctxt);
|
||||
extern rtl_opt_pass *make_pass_regrename (gcc::context *ctxt);
|
||||
|
|
|
|||
Loading…
Reference in New Issue